Self-Aligned Via Formation in Interconnect Structures

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Solution Overview

Problem

Conventional semiconductor fabrication techniques face challenges in reducing via resistance and preventing via-metal shorts as metal pitch is scaled down, leading to increased signal delay and electrical shorts between metal lines in integrated circuits.

Innovation Solution

The formation of self-aligned vertical interconnects (vias) within recess areas in the underlying metal lines, using a stop layer and conductive material deposition to align vias precisely with both underlying and overlying metal lines, thereby reducing misalignment and increasing the distance between vias and adjacent metal lines to prevent shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If metal pitch is scaled down to reduce interconnect size, then device size is reduced, but via resistance increases due to misalignment and signal delay increases

Engineering Contradiction:
Improvedevice sizeVSAvoidvia resistance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The via formation process uses the upper metal line pattern itself as the alignment reference for etching the via hole. The via is etched to be self-aligned with the upper metal line, eliminating the need for separate alignment processes and ensuring precise alignment that reduces via resistance even at scaled dimensions

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The upper metal line is formed first before the via is created. This preliminary formation establishes the alignment reference that guides subsequent via etching, ensuring the via will be properly positioned to minimize resistance before the actual via formation occurs

Inventive Principle:
Principle #10Preliminary action

2Volume of moving object

If metal pitch is scaled down to reduce interconnect size, then device size is reduced, but via-metal short distance decreases causing electrical shorts

Engineering Contradiction:
Improvedevice sizeVSAvoidvia-metal short
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The via alignment is determined by the upper metal line pattern itself rather than by separate alignment processes. This self-aligned approach ensures consistent spacing between the via and lower metal lines, maintaining adequate via-metal short distance even when overall metal pitch is reduced

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The upper metal line pattern is established beforehand to serve as the alignment template. This preliminary pattern formation ensures that subsequent via etching will naturally maintain proper spacing from lower metal lines, preventing shorts even at reduced pitch dimensions

Inventive Principle:
Principle #10Preliminary action

3Reliability

If via alignment to underlying metal line is improved to reduce via resistance, then via resistance decreases, but manufacturing complexity increases due to alignment precision requirements

Engineering Contradiction:
Improvevia resistanceVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via alignment is achieved through self-alignment where the upper metal line pattern automatically serves as the reference for via positioning. This eliminates complex multi-step alignment procedures and reduces manufacturing complexity while ensuring precise via alignment to minimize resistance

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The via formation process is merged with the upper metal line pattern formation. By using the same patterning process for both the upper metal line and via alignment reference, the invention combines multiple functions into a single process step, reducing overall manufacturing complexity

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3433877B1Forming self-aligned vertical interconnect accesses in interconnect structures for integrated circuits
Publication Date: 2022.07.06 QUALCOMM INC
  • EP3433877B1 patent drawingFigure 1A~1B
  • EP3433877B1 patent drawingFigure 2A~2B
  • EP3433877B1 patent drawingFigure 3A

AI summary

Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.