Self-Aligned Via Structure for Overlay-Error-Free Interconnects
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Solution Overview
Problem
In semiconductor device fabrication, the formation of vias between metal lines is challenging due to overlay errors and edge placement errors, leading to increased via resistance and potential shorting issues.
Innovation Solution
A semiconductor interconnect structure is developed where a via is self-aligned to both a lower level metal line and an upper level metal line, eliminating overlay errors and edge placement errors through a specific method of forming hard masks and selectively etching to create aligned openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via formation processes are used, then manufacturing simplicity is maintained, but overlay errors and edge placement errors increase leading to poor via alignment
Solution Approach 1:
The method performs preliminary actions by forming the first hard mask on the lower metal line before forming the upper metal line. This hard mask serves as a pre-established reference structure that guides subsequent etching operations, ensuring the via is self-aligned to the lower metal line before the upper metal line is even formed.
Solution Approach 2:
The first hard mask acts as an intermediary structure between the lower and upper metal lines. It mediates the alignment relationship by providing a physical reference that the via etching process can directly follow, eliminating the need for separate alignment operations between the two metal layers.
2Reliability
If self-aligned via structure is implemented, then via resistance is reduced and shorting is eliminated, but manufacturing process complexity increases
Solution Approach 1:
The via structure is self-aligned through the process design, meaning the via automatically positions itself relative to both metal lines through the etching sequence rather than requiring separate alignment operations. The process serves its own alignment function through the sequential exposure and etching of hard mask layers.
Solution Approach 2:
The process segments the via formation into distinct etching stages: first etching through the upper metal line to expose the lower hard mask, then etching through the lower hard mask to complete the via. This segmentation allows each etching operation to focus on a specific alignment task, improving overall precision.
3Manufacturing precision
If multiple etching steps are used for self-alignment, then via alignment precision improves, but manufacturing time increases
Solution Approach 1:
The method merges multiple alignment functions into a unified process flow. The first hard mask simultaneously serves as the alignment reference for both the via etching and the upper metal line formation, combining what would traditionally require separate alignment operations into a single integrated process sequence.
Solution Approach 2:
The preliminary formation of the first hard mask with specific dimensional relationships to both metal lines allows subsequent etching operations to proceed without additional alignment steps. The preliminary structure encodes the alignment information that guides the entire via formation process.
Data Source
AI summary
A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a lower level metal line extending along a first direction. The semicondutor interconnect structure further includes an upper level metal line extending along a second direction, where the upper level metal line includes a first portion and a second portion. The semiconductor interconnect structure further includes a via formed on top of the lower level metal line and interconnecting the lower level metal line to the upper level metal line. The via is self-aligned to the lower level metal line along the second direction and self-aligned to the upper level metal line along the first direction.