Self-Aligned Via Landing Structure for Low-Resistance Interconnects
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Solution Overview
Problem
Existing semiconductor fabrication processes face challenges in achieving reduced contact resistance and consistent via landing, particularly in smaller semiconductor devices with pitches less than 20 nanometers, leading to variations in via widths and increased metal leak space.
Innovation Solution
The formation of a recess in a metal layer during fabrication, coupled with the use of an etch stop layer and conductive vias that extend below the dielectric layer, allows for improved via landing and reduced contact resistance, achieved through processes like wet etching and deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but via width variations increase and contact resistance increases
Solution Approach 1:
The etch stop layer is formed over the metal layer before via etching, creating a predetermined landing zone that guides via formation. This preliminary structural preparation ensures consistent via widths and proper via landing on the metal layer, resolving the contradiction between via width consistency and process complexity.
Solution Approach 2:
The etch stop layer acts as an intermediary between the metal layer and the dielectric layer, providing a controlled interface for via formation. This intermediary layer enables precise via landing and width control without requiring complex fabrication processes, as it naturally defines the via landing zone through its positioning and etch characteristics.
2Length of moving object
If via size is reduced for smaller devices, then device pitch is reduced, but contact resistance increases
Solution Approach 1:
The etch stop layer creates a localized enlarged via landing zone specifically at the via bottom where contact with the metal layer occurs. This local enlargement at the contact point maintains low contact resistance even when the overall via size is reduced for smaller device pitches, resolving the contradiction between reduced pitch and contact resistance.
3Ease of manufacture
If etch stop layer is completely removed, then via landing is simplified, but via width control precision decreases
Solution Approach 1:
The etch stop layer is partially removed through the via etch process rather than being completely removed or left intact. This partial removal exposes the metal layer at the via bottom for proper contact while maintaining the layer's presence in surrounding areas to define via width, resolving the contradiction between via landing simplicity and via width control precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variations in via widths, enlarges via sizes, and controls overlap, resulting in lower contact resistance and improved performance in semiconductor devices, especially in small-pitch applications.
Implementation Method 1
The etch stop layer can be formed using a thin layer of aluminum oxide and can be partially removed using a wet etching process during the fabrication process
Data Source
AI summary
A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.