Self-Aligned Interconnect Scheme for Via-to-Line Breakdown
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Solution Overview
Problem
Aggressive scaling down of IC dimensions leads to challenges in controlling the distance between conductive features, resulting in via-to-line breakdown and increased parasitic capacitance, which affects the reliability and performance of semiconductor devices.
Innovation Solution
A self-aligned scheme is introduced, where a dielectric SAS layer is deposited over the lower level dielectric layer without touching the lower level conductive feature, blocking the higher level conductive feature from breaking down and allowing it to land on both the lower level conductive feature and the SAS layer, thereby increasing the distance between them, and an extra recessing process is performed to further enlarge this distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing precision deteriorates due to difficulties in controlling the distance between conductive features
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the lower level conductive feature and the higher level conductive feature. This dielectric layer acts as a mediator that ensures proper spacing and alignment, preventing direct contact while maintaining the scaled-down dimensions. The dielectric layer is deposited conformally and then planarized to provide a controlled interface between conductive features at different levels.
Solution Approach 2:
The dielectric layer is deposited and planarized before forming the higher level conductive feature. This preliminary action establishes the proper spacing and alignment conditions in advance, ensuring that when the higher level conductive feature is formed, the distance control requirements are already satisfied by the pre-prepared dielectric layer structure.
2Productivity
If the distance between conductive features is reduced to increase pattern density, then productivity improves, but reliability deteriorates due to via-to-line breakdown
Solution Approach 1:
The dielectric layer serves as a protective intermediary that physically separates the lower level conductive feature from the higher level conductive feature. This intermediary layer prevents direct contact between conductors that would cause breakdown, while still allowing the features to be positioned close together for high pattern density.
Solution Approach 2:
The dielectric layer is deposited beforehand to create a protective cushion or barrier between conductive features. This pre-established dielectric barrier provides insulation and prevents breakdown before any electrical stress occurs, cushioning against potential failure modes.
3Productivity
If the distance between conductive features is reduced to increase pattern density, then productivity improves, but parasitic capacitance increases
Solution Approach 1:
The dielectric layer acts as an intermediary that provides electrical insulation between closely spaced conductive features. By maintaining proper spacing through this dielectric barrier, the parasitic capacitance between adjacent conductors is reduced compared to what would occur if the features were in direct contact or separated only by air.
Solution Approach 2:
The dielectric layer changes the electrical parameters of the structure by providing a controlled dielectric medium between conductors. This parameter change affects the capacitance characteristics, allowing for optimized electrical performance while maintaining high pattern density through controlled material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates via-to-line breakdown, reduces parasitic capacitance, and improves the performance of semiconductor devices by ensuring reliable interconnects and higher pattern density.
Implementation Method 1
a dielectric SAS layer is deposited over the lower level dielectric layer
Implementation Method 2
a dielectric SAS layer is deposited over the lower level dielectric layer
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.