Self-Aligned Via and Metal Line Interconnect Structure
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to enhance via-to-line overlay performance and prevent void formation in vias as semiconductor devices scale down, requiring improved methods for forming interconnect structures that maintain low resistance and resistance-capacitive delay while ensuring robustness against voltage breakdown and time-dependent dielectric breakdown.
Innovation Solution
The method involves forming a second metal material over a first metal material and using the same mask element to etch both, allowing for self-aligned via and metal line formation, which enhances overlay performance and reduces the likelihood of voids by depositing and etching the second metal material, resulting in low-resistance metal lines and vias with improved contact resistance and breakdown capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase device density, then device density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the via formation and metal line formation processes into a single etching step using a common mask element. This merging of operations reduces the number of separate manufacturing steps required, thereby decreasing manufacturing process complexity while maintaining the ability to form multi-layered interconnect structures at scaled dimensions for increased device density
2Adaptability or versatility
If conventional separate etching processes are used for via and metal line formation, then process flexibility is maintained, but via-to-line overlay performance deteriorates
Solution Approach 1:
The common mask element serves itself for dual purposes: it defines both the via openings and the metal line patterns in a single etching process. This self-aligning mechanism eliminates the need for separate masking and alignment steps, achieving superior via-to-line overlay performance while maintaining process flexibility through the unified mask design
3Ease of manufacture
If traditional via formation methods are used, then manufacturing simplicity is maintained, but void formation occurs in vias
Solution Approach 1:
The metal material is deposited conformally over the entire surface including the via regions before the etching step. This preliminary deposition ensures that metal is present in the via openings before any removal occurs, and the subsequent etching through the common mask element creates clean via openings without void formation, maintaining manufacturing simplicity while improving via reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances via landing area, reduces contact resistance, and eliminates voids in vias, leading to improved semiconductor device performance with reduced sheet resistance and enhanced voltage and time-dependent dielectric breakdown resistance.
Implementation Method 1
etching the second metal material and the first metal material using the same mask element to form a via and a metal line respectively
Implementation Method 2
forming a second metal material over a first metal material
Data Source
AI summary
A method for forming an interconnect structure is provided. The method for an interconnect structure includes forming a first metal material over a semiconductor substrate, and forming a first mask element over the first metal material. The first mask element has an opening through the first mask element. The method for forming the interconnect structure also includes forming a second metal material over the first mask element and the first metal material and in the opening, and forming a second mask element corresponding to the opening and over the second metal material. The method for forming the interconnect structure also includes etching the second metal material and the first metal material using the second mask element and the first mask element to form a via and a first metal line respectively.