Self-Aligned Via Formation Using Notched Hard Masks
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Solution Overview
Problem
In back end of line (BEOL) patterning for integrated circuits, the formation of vias can result in 'blow-out' regions, leading to reduced insulation between metal lines and potential short circuits or defects, especially at smaller feature sizes, where lithographic limitations make it challenging to maintain via diameter and yield.
Innovation Solution
The method involves depositing a dielectric mask and a hard mask over a metal layer on a semiconductor wafer, forming a lithographic pattern with notched areas, and etching vias adjacent to or within these notches to minimize 'blow-out' regions by creating a tapered etch that maintains a consistent line width, preventing vias from extending past metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithographic patterning is used to form vias, then the via formation process is simple, but 'blow-out' regions occur leading to reduced insulation and potential short circuits
Solution Approach 1:
The patent applies preliminary action by forming notched areas in the hard mask layer before via etching. These notches are pre-positioned to control the via placement and prevent blow-out regions during the etching process, thereby ensuring proper insulation between metal lines while maintaining manufacturing precision
Solution Approach 2:
The patent introduces an intermediary structure - the notched hard mask - that mediates between the lithographic pattern and the final via formation. The notches act as a physical guide that constrains the etch process, preventing excessive via extension and ensuring precise via placement without requiring complex lithographic modifications
2Reliability
If via diameter is reduced to maintain insulation, then insulation between metal lines is improved, but manufacturing yield decreases due to lithographic limitations
Solution Approach 1:
The notched areas are formed in advance in the hard mask layer, allowing larger vias to be etched while still maintaining proper insulation. This preliminary structuring of the mask enables via dimensions that are achievable with current lithographic capabilities, thereby maintaining manufacturing yield while ensuring reliable insulation
3Adaptability or versatility
If staggered configuration of vias is used, then the basic BEOL design construct is maintained, but imaging becomes challenging at smaller feature sizes
Solution Approach 1:
The notched hard mask serves as an intermediary that simplifies the imaging process. The notches create distinct, well-defined features that are easier to image and align than traditional staggered via configurations, thereby reducing imaging difficulty while maintaining the necessary BEOL design flexibility through the staggered via placement within the notched regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the occurrence of 'blow-out' areas, ensuring proper insulation and preventing short circuits, while adhering to lithographic limitations and maintaining manufacturing yield by maintaining consistent line widths and avoiding excessive via extension.
Implementation Method 1
A dielectric mask is deposited over a metal layer. A hard mask is deposited over the dielectric layer.
Implementation Method 2
A lithographic pattern is formed over the hard mask. The lithographic pattern contains lines with notched areas.
Implementation Method 3
A via is etched in one of the one or more notched areas of the lithographic pattern.
Data Source
AI summary
A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.