Self-Aligned Via Patterning for BEOL Interconnects
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Solution Overview
Problem
The scaling of features in integrated circuits poses challenges in via manufacturing, particularly with extremely small via pitches and critical dimensions, as existing lithographic processes struggle to maintain overlay tolerances, resolution capabilities, and line width roughness/critical dimension uniformity, leading to increased costs and potential limitations in printing via openings.
Innovation Solution
A self-aligned via and plug patterning method using directed self-assembly and selective growth mechanisms, where an underlying metal layer serves as a template to guide the formation of vias and metal lines, reducing reliance on lithography for alignment and improving electrical contact by building features from the previous layer up, thereby simplifying lithography photoresist design and reducing process operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern vias with extremely small pitches and critical dimensions, then via opening formation is achieved, but overlay tolerances cannot be maintained and resolution capabilities are exceeded
Solution Approach 1:
The patent applies preliminary action by forming mandrel structures and spacer layers before the final via patterning step. The mandrels are positioned with relaxed tolerances, and spacers are deposited conformally to define the final via locations with high precision, enabling sub-35nm critical dimensions while maintaining overlay tolerances that are quarter of the via pitch or less
Solution Approach 2:
The patent uses spacer layers as intermediary structures between the mandrel pattern and the final via openings. These spacers act as a mediator that transfers the pattern from the mandrels to the via holes, enabling precise via placement without requiring direct lithographic patterning at the final critical dimension, thus resolving the resolution capability limitation
2Length of moving object
If shrink technologies are applied to reduce via critical dimensions, then smaller via openings are achieved, but minimum via pitch and line width roughness/critical dimension uniformity are compromised
Solution Approach 1:
The patent replaces the mechanical shrink process with a self-aligned spacer formation process. Instead of using shrink technologies that physically compress the pattern, the method uses conformal spacer deposition and anisotropic etching to define via locations, achieving sub-35nm critical dimensions without the line width roughness and critical dimension uniformity degradation associated with shrink processes
Solution Approach 2:
The patent changes the physical and chemical parameters of the spacer materials and deposition conditions to achieve precise via patterning. By controlling spacer thickness, composition, and deposition parameters, the method achieves consistent sub-35nm via critical dimensions with improved line width roughness and critical dimension uniformity compared to shrink technologies
3Manufacturing precision
If multiple lithographic masks are used to print extremely small via pitches, then via opening formation is achieved, but manufacturing costs increase
Solution Approach 1:
The patent uses preliminary mandrel formation with relaxed pitch requirements, followed by spacer deposition to achieve the final sub-70nm via pitch. This preliminary patterning step allows using a single lithographic mask or fewer masks compared to direct multi-patterning approaches, reducing manufacturing costs while achieving the required via pitch precision
Solution Approach 2:
The patent segments the via patterning process into distinct stages: mandrel formation, spacer deposition, and via etching. This segmentation allows each step to be optimized independently, with the mandrel step using relaxed tolerances and the spacer step providing the final precision, thereby reducing the need for multiple expensive lithographic masks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more robust interconnect fabrication with improved electrical contact, reduced processing time, and increased tolerance in via and plug selection, allowing for the fabrication of smaller features with enhanced precision and reduced costs.
Implementation Method 1
The directed self-assembly of the block copolymer layer portion includes inducing microphase separation of the block copolymer molecules
Implementation Method 2
The condensation reaction of the unsaturated silane-modified low-k material is initiated by a vapor deposited catalyst layer
Data Source
AI summary
Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.