Self-Aligned Via Patterning for BEOL Interconnects
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in patterning extremely small vias with tight pitches, as they require precise overlay control and resolution capabilities that are beyond the limits of existing lithographic technologies, leading to increased costs and potential inability to print via openings for extremely small pitches using EUV scanners.
Innovation Solution
The implementation of subtractive self-aligned via and plug patterning methods, which pre-form vias and plugs using trenches and utilize photobuckets for selective retention, simplifying overlay errors and reducing reliance on lithography for alignment, thereby enabling more robust interconnect fabrication with improved electrical contact and reduced process operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern vias, then via openings can be formed, but overlay control becomes increasingly difficult as via pitch decreases to 70nm or less
Solution Approach 1:
The patent applies preliminary action by pre-forming trenches and filling them with conductive material before final via patterning. This creates a self-aligned structure where the via location is predetermined by the trench position, eliminating the need for precise lithographic overlay control at subsequent steps. The trench formation and fill occur before the final via opening definition, ensuring alignment without requiring high-precision overlay at the via patterning stage.
Solution Approach 2:
The patent inverts the conventional approach by using a subtractive process rather than additive. Instead of directly patterning via openings through lithography, the method forms trenches, fills them, and then selectively removes material to define final via locations. This inversion transforms the problem from requiring precise positive patterning to requiring precise negative patterning and selective removal, where self-alignment provides the precision.
2Manufacturing precision
If via critical dimensions are reduced to maintain scaling, then device density increases, but critical dimension uniformity deteriorates faster than lithographic resolution improves
Solution Approach 1:
The patent establishes the via location and dimensions through preliminary trench formation and filling operations. The trench depth, width, and position are controlled during the trench formation step, and the conductive fill is deposited to match these pre-defined dimensions. This preliminary definition of via geometry removes the dependency on final lithographic patterning for critical dimension control, allowing CD uniformity to be maintained through the more controllable trench formation process rather than being limited by lithographic resolution improvements.
3Manufacturing precision
If multiple lithographic masks are used to pattern extremely small pitches, then via openings can be formed, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses preliminary action to form trenches and fill them with conductive material before final via definition. This pre-established structure serves as a template that guides subsequent selective removal steps. By having the via locations predetermined by the trench network, the final patterning step only requires selective removal at specific locations rather than using multiple complex lithographic masks to define each via location from scratch.
Solution Approach 2:
The patent introduces an intermediary structure (the filled trench network) that mediates between the initial substrate and the final via pattern. This intermediary serves as a self-aligned template that simplifies the final patterning step. The trench fill acts as a mediator that carries the positional information forward, allowing subsequent selective removal to define vias without requiring complex direct lithographic patterning of each via location.
4Quantity of substance
If via sizes are reduced to increase device density, then capacity increases, but overlay tolerances must be controlled at even greater rates than lithographic equipment can maintain
Solution Approach 1:
The patent applies preliminary action by pre-forming the trench network that defines all via locations before final via patterning. This preliminary structure establishes a self-aligned reference framework that determines via positions independently of subsequent lithographic overlay. The trench formation and fill create a physical template that guides where vias will be formed, allowing high device density through small via spacing without requiring proportionally tighter overlay tolerances at each patterning step.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.