Self-Aligned Via Recessing for Overlay-Free Interconnects
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving fully aligned vertical metal line interconnects (vias) due to high aspect ratios and overlay errors, leading to issues like electro-migration and time-dependent dielectric breakdown, particularly in reducing via size variation and maintaining electrical field control.
Innovation Solution
A selective recess process is employed to form metal lines in a first dielectric layer, where portions are recessed below the surface, allowing for a via to be aligned in a selective recess region without relying on hard mask overlay, using a cap and etch-resistant dielectric to self-align the via perpendicularly to interconnect layers, reducing aspect ratios and improving metal fill and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form vias, then the via alignment depends on hard mask overlay, but this leads to via size variation and reliability issues due to high aspect ratios and overlay errors
Solution Approach 1:
The via formation process uses self-aligned recesses created by the metal lines themselves as the reference structure. The recesses are formed by etching the dielectric layer around the metal lines, automatically positioning the via openings aligned with the metal lines without requiring additional overlay steps. This self-service mechanism eliminates overlay errors and improves via alignment precision while enhancing device reliability
Solution Approach 2:
The method performs preliminary recess formation of the dielectric layer around metal lines before via opening. By pre creating the recess structures that define the via locations and dimensions, the process establishes precise alignment references in advance, eliminating the need for subsequent overlay-dependent alignment steps and reducing via size variation
2Productivity
If via size is reduced to increase device density, then more devices can be fabricated on a single wafer, but electro-migration and dielectric breakdown risks increase
Solution Approach 1:
The invention changes the geometric parameters of the via structure by forming recesses in the dielectric layer that create larger via openings with reduced aspect ratios. This parameter change allows smaller via footprints while maintaining adequate via dimensions for reliable current flow, enabling higher device density without increasing electro-migration or dielectric breakdown risks
Solution Approach 2:
The method introduces vertical dimensionality by forming recesses at different depths around metal lines. This dimensional approach creates via openings that are larger in the horizontal plane (reducing aspect ratio) while maintaining compact overall via footprint, allowing increased device density while preserving electrical reliability through improved current distribution
3Ease of manufacture
If hard mask overlay is used for via alignment, then the process follows conventional fabrication steps, but overlay errors cause via misalignment and manufacturing defects
Solution Approach 1:
The process uses the metal lines and their surrounding recesses as self-aligned references for via formation. The recesses are automatically positioned by the metal line locations through the etching process, eliminating the need for separate hard mask alignment steps. This self-service approach maintains fabrication simplicity while achieving superior via alignment accuracy without overlay errors
Solution Approach 2:
The recess structure serves as an intermediary element that mediates between the metal lines and the via openings. By forming recesses that extend from the metal lines to define via locations, the process creates a intermediate reference structure that automatically ensures precise via alignment without requiring hard mask overlay, simplifying the fabrication process while improving alignment accuracy
Data Source
AI summary
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.