Self-aligned via interconnects using relaxed patterning exposure
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Solution Overview
Problem
Conventional via interconnect processes in integrated circuits face challenges due to small via size, high density, and alignment requirements, leading to increased costs and limitations in line-pattern density.
Innovation Solution
The implementation of self-aligned via interconnects using a 'generous via' pattern that allows for relaxed patterning exposure, where the via pattern is imprecise and indicates general areas for via formation, reducing the need for critical alignment and dimensional control, and is compatible with existing integrated circuit design and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic via patterning is used with precise alignment, then via placement accuracy is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The via pattern automatically defines its own placement locations through the self-aligned via formation process. The imprecise via pattern serves as a guide for subsequent self-aligned processing steps, eliminating the need for separate alignment operations and complex lithographic patterning while maintaining accurate via placement.
2Manufacturing precision
If conventional lithographic via patterning is used with precise alignment, then via placement accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses an imprecise via pattern that does not require expensive, high-precision lithographic equipment. The pattern is intentionally designed with relaxed dimensional requirements, allowing the use of simpler, less costly patterning tools while still achieving the desired via placement through self-aligned processing.
3Reliability
If minimum via spacing is increased for alignment tolerance, then alignment robustness is improved, but line-pattern density decreases
Solution Approach 1:
The patent transitions from two-dimensional planar alignment to three-dimensional self-aligned via formation. By utilizing vertical layering and self-aligned processing, the system achieves robust via placement without being constrained by increased minimum spacing in the planar domain, thereby maintaining high line-pattern density.
Data Source
AI summary
Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.