Self-Aligned Interconnect Via Formation for Nanometer Routing
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Solution Overview
Problem
Traditional lithography and etch processes struggle to ensure accurate alignment between vias and underlying and overlying conductive lines as semiconductor dimensions shrink, posing challenges in interconnect routing, particularly in 2-dimensional layouts, and existing methods like photobuckets and block copolymers are not scalable to nanometer pitch dimensions.
Innovation Solution
A method involving the use of different interlayer dielectric materials that are selectively etchable, allowing for the formation of self-aligned interconnect vias by etching and masking techniques, ensuring alignment to the width of lower and upper conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography and etch processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates as dimensions shrink
Solution Approach 1:
The patent applies preliminary action by forming the first interlayer dielectric layer and etch stop layer before creating the via opening. The etch stop layer is deposited in advance to define the precise depth termination point for via etching, ensuring accurate alignment with the lower conductive line before the actual via formation occurs. This pre-positioning of the etch stop layer enables precise depth control without requiring complex real-time monitoring during etching.
Solution Approach 2:
The patent implements self-service through self-aligned processes where the via opening is automatically positioned relative to the conductive lines through the use of the etch stop layer and interlayer dielectric materials. The selective etching of the first interlayer dielectric layer reveals the etch stop layer, which in turn defines the via depth and position, eliminating the need for separate alignment steps and reducing process complexity while maintaining high precision.
2Manufacturing precision
If existing methods like photobuckets or block copolymers are used, then via alignment is improved, but scalability to nanometer pitch dimensions deteriorates
Solution Approach 1:
The patent applies parameter changes by utilizing the etch selectivity between different materials (first interlayer dielectric layer versus second interlayer dielectric layer and etch stop layer) to achieve precise via formation. By changing the material parameters and their etch selectivity relationships, the process achieves high alignment precision that can be scaled to nanometer pitch dimensions, overcoming the limitations of photobucket and block copolymer methods.
Solution Approach 2:
The patent implements segmentation by dividing the interlayer dielectric structure into distinct layers with different etchability characteristics. The first interlayer dielectric layer is selectively removed to form via openings, while the second interlayer dielectric layer and etch stop layer remain intact to define the via position and depth. This segmented approach enables precise via alignment that is scalable to advanced nanometer pitch dimensions.
3Area of stationary object
If tip-to-tip spacing between conductive lines is reduced, then chip surface area is decreased, but alignment difficulty increases
Solution Approach 1:
The patent implements self-service through self-aligned via formation where the via position is automatically determined by the underlying conductive line structure and etch stop layer configuration. This self-alignment mechanism eliminates the need for complex lithographic alignment steps, enabling precise via placement even when tip-to-tip spacing is reduced to minimize chip surface area.
Solution Approach 2:
The patent applies preliminary action by pre-forming the etch stop layer and interlayer dielectric structures before via etching. These preliminary structures serve as built-in alignment references that automatically define the via position relative to the conductive lines, enabling precise alignment even at reduced tip-to-tip spacing without requiring additional alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of self-aligned interconnect vias that connect transversely oriented conductive lines, facilitating tight tip-to-tip spacing and scalable fabrication even at nanometer dimensions, thereby improving semiconductor processing flexibility.
Implementation Method 1
a first interlayer dielectric material... an etch stop layer... a second interlayer dielectric material, the second interlayer dielectric material being selectively etchable with respect to the first interlayer dielectric material and vice versa
Data Source
AI summary
A method includes: producing on a substrate a stack of: a first layer including a first dielectric material, a second layer including dielectric material on the first layer, and an etch stop layer between the first layer and the second layer, etching a trench through the second layer, the etch stop layer, and the first layer, producing a lower conductive line in the trench, producing a third layer including a second dielectric material in the trench and on the tower conductive line, removing a first portion of the second layer, such that a second portion of the second layer remains in contact with the etch stop layer, etching a via opening through the third layer in the trench, using the second portion of the second layer as a mask, and depositing a conductive upper line and an interconnect via on the lower conductive line within the via opening.