Self-Aligned Via Formation Using Selective Dielectric Deposition
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Solution Overview
Problem
As semiconductor devices miniaturize, misalignment issues in multilayer interconnects (MLI) structures become more pronounced, leading to defects, reliability issues, and increased complexity in manufacturing due to overlay errors during lithography processes, which can result in via misalignment and excessive etching.
Innovation Solution
A method for fabricating semiconductor devices that involves forming a first dielectric layer selectively over conductive lines, using a pre-treatment and treatment process to create an inhibitor film, and then depositing a second dielectric layer with etch selectivity to alleviate the need for precise alignment, allowing for self-alignment of via openings and improved etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography alignment processes are used, then manufacturing complexity is reduced, but misalignment errors increase leading to defects and reliability issues
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and applying a first dielectric layer with specific etch selectivity before the via etching process. This pre-prepared structure serves as a self-aligning template that guides subsequent via formation, eliminating the need for high-precision lithography alignment while preventing misalignment defects.
Solution Approach 2:
The patent introduces an intermediary mandrel structure and first dielectric layer that act as a mediator between the lithography pattern and the final via structure. This intermediary layer with controlled etch selectivity translates the lithography pattern into precisely aligned vias without requiring direct high-precision alignment, thus reducing both misalignment errors and processing complexity.
2Reliability
If precise alignment is required for via formation, then overlay errors are minimized, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent implements self-service through self-aligned via formation where the via etch process automatically aligns to the underlying conductive feature using the mandrel and first dielectric layer as a self-aligning template. The etch selectivity of the first dielectric layer ensures the via opens precisely at the intended location without requiring external alignment control, thereby improving reliability while simplifying manufacturing.
Solution Approach 2:
The patent changes the etch selectivity parameter of the first dielectric layer relative to the second dielectric layer to enable self-aligned via formation. By controlling this parameter, the via etch process selectively removes the first dielectric layer to expose the conductive feature while leaving the second dielectric layer intact, achieving precise alignment without complex manufacturing procedures.
3Manufacturing precision
If overlay window is enlarged to tolerate misalignment, then manufacturing precision requirements are relaxed, but etching selectivity control becomes more difficult
Solution Approach 1:
The patent segments the dielectric structure into a first dielectric layer with high etch selectivity and a second dielectric layer with low etch selectivity. This segmentation allows the via etch process to selectively remove only the first dielectric layer while preserving the second layer, enabling precise via formation with an enlarged overlay window without increasing etching process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of misalignment and excessive etching, providing a larger overlay window for via formation and improving device performance by enhancing contact area and reducing contact resistance.
Implementation Method 1
a first dielectric layer is selectively formed over the conductive line
Implementation Method 2
using a pre-treatment and treatment process to create an inhibitor film
Implementation Method 3
depositing a second dielectric layer with etch selectivity
Data Source
AI summary
Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.