Self-Aligned Interconnect Scheme for Via-to-Line Spacing
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Solution Overview
Problem
Aggressive scaling down of IC dimensions in semiconductor manufacturing leads to challenges in controlling the distance between conductive features, resulting in via-to-line breakdown and increased parasitic capacitance, which affects device reliability and performance.
Innovation Solution
A self-aligned scheme is introduced, where a dielectric SAS layer is deposited over the lower level dielectric layer without touching the lower level conductive feature, and a higher level conductive feature is formed with a portion landing on this SAS layer, thereby increasing the distance between adjacent conductive features and mitigating breakdown issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing precision deteriorates due to difficulties in controlling the distance between conductive features
Solution Approach 1:
A dielectric layer is deposited in advance over the lower level dielectric layer before forming the higher level conductive feature. This preliminary dielectric layer serves as a buffer that ensures adequate spacing between conductive features at different levels, preventing via-to-line breakdown even as dimensions are scaled down for improved productivity
Solution Approach 2:
The dielectric layer acts as an intermediary element between the lower level dielectric layer and the higher level conductive feature. This intermediate layer provides the necessary electrical isolation and spacing control, enabling continued scaling while maintaining manufacturing precision
2Adaptability or versatility
If IC dimensions are scaled down to increase device functionality, then adaptability improves, but reliability deteriorates due to via-to-line breakdown and increased parasitic capacitance
Solution Approach 1:
The dielectric layer is deposited beforehand to establish proper spacing and electrical isolation before the higher level conductive feature is formed. This preliminary structure prevents via-to-line breakdown and reduces parasitic capacitance, maintaining reliability as devices are scaled to support more functions
Solution Approach 2:
The dielectric layer provides localized electrical isolation and spacing control at critical interfaces between conductive features. By enhancing the dielectric properties at this specific location, the patent prevents breakdown paths and reduces parasitic capacitance without affecting overall device functionality
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.