Self-Aligned Via and Trench Formation in Semiconductor Structures
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Solution Overview
Problem
The existing methods for forming aligned trenches and vias in semiconductor structures face challenges with misalignment, which affects the density and yield of semiconductor circuits, leading to poorer production quality and increased complexity.
Innovation Solution
A multi-layer semiconductor structure is formed with specific stop layers and photoresist patterns to accurately etch via and trench patterns, ensuring precise alignment and filling with conductive material, reducing misalignment and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a critical dimension is used to assure proper alignment between vias and trenches, then alignment precision is improved, but circuit density is reduced
Solution Approach 1:
The patent segments the via formation process into multiple steps: first forming vias through the first stop layer, then forming trenches through the second stop layer, and finally forming a second set of vias through the third stop layer. This segmentation allows each layer to be optimized independently, achieving proper alignment without requiring an overly restrictive critical dimension that would limit circuit density.
Solution Approach 2:
The patent introduces multiple stop layers at different vertical levels (first, second, and third stop layers) to control alignment in the vertical dimension. By using these stacked stop layers, the patent achieves precise alignment control without relying solely on horizontal critical dimension constraints, thereby allowing higher circuit density while maintaining alignment precision.
2Manufacturing precision
If multiple stop layers and photoresist patterns are used to ensure precise alignment, then manufacturing precision is improved, but process complexity is increased
Solution Approach 1:
The patent divides the alignment control into segmented steps using multiple stop layers, where each stop layer handles a specific alignment task. This segmentation makes the complex alignment process more manageable and controllable, achieving high precision without requiring an overly complex monolithic process.
Solution Approach 2:
The patent performs preliminary actions by forming the first set of vias and first set of trenches before forming the second set of vias. This preliminary action establishes reference structures that guide subsequent formation steps, simplifying the overall alignment process while maintaining high precision.
3Manufacturing precision
If via and trench patterns are formed in separate steps, then alignment precision is improved, but production time is increased
Solution Approach 1:
The patent performs preliminary formation of vias and trenches in the first and second stop layers before final via formation. This preliminary action creates reference structures that accelerate the final alignment step, achieving high precision without excessive production time delay.
Solution Approach 2:
The patent implements a nested structure where the first set of vias and trenches are formed within the context of subsequent via and trench formation steps. This nesting allows multiple alignment functions to be performed in an integrated manner, reducing total production time while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces misalignment issues, improves device performance by lowering contact resistance, increases production yield, and allows for smaller circuit designs while simplifying the process and reducing costs.
Implementation Method 1
A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns
Implementation Method 2
The structure is etched to form the via pattern in the third stop layer through the fourth stop layer. The structure is then etched until all of the via-trench portions reach the metal line
Data Source
AI summary
A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.