Self-Aligned Vias and Air-Gaps for Precise Semiconductor Patterning
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Solution Overview
Problem
Existing methods struggle to fabricate self-aligned vias and air-gaps in semiconductor fabrication due to the increased complexity and reduced dimensions of components, making it difficult to align inline vias, line-end vias, and air-gaps with semiconductor structures.
Innovation Solution
A method involving etching trenches at specific locations through mask layers, forming via structures using removable materials, and filling trenches with conductive metal to create self-aligned line-end and inline vias, while aligning air-gaps with these vias, and using low resistance materials to encapsulate hollow spaces for air-gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography methods are used to fabricate vias and air-gaps, then the manufacturing process is simpler, but the alignment precision between vias, air-gaps, and semiconductor structures deteriorates due to increased complexity and reduced dimensions
Solution Approach 1:
The patent applies preliminary action by forming mandrels and spacers before the actual via formation process. The mandrels are deposited and patterned first, then spacers are formed around them, creating a self-aligned structure that guides subsequent via etching. This preliminary structuring ensures precise alignment without requiring complex alignment steps during via fabrication.
Solution Approach 2:
The patent uses mandrels and spacers as intermediary structures to achieve precise alignment. The mandrels serve as temporary structures that define the position of spacers, which in turn define the via locations. These intermediary elements mediate the alignment between different features, allowing precise positioning without direct alignment between final structures.
2Productivity
If component dimensions are reduced to increase integration density, then the quantity of components increases, but the difficulty of aligning vias and air-gaps with semiconductor structures increases
Solution Approach 1:
The patent implements self-service through self-aligned via formation where the via positions are automatically determined by the spacer structures. The spacers, formed around mandrels, serve as self-aligned masks that define via locations without requiring external alignment steps. This self-service mechanism ensures precise alignment even as dimensions are reduced and integration density increases.
Solution Approach 2:
The patent transitions from two-dimensional planar alignment to three-dimensional self-aligned structuring. By forming vertical spacers around mandrels and using them as masks for via etching, the alignment is achieved in the vertical dimension rather than relying on planar alignment. This dimensional transition enables precise positioning at reduced scales.
3Manufacturing precision
If self-aligned vias and air-gaps are fabricated using the patent method, then alignment precision improves, but the number of fabrication steps increases
Solution Approach 1:
The patent merges multiple functions into the spacer structures. The spacers serve simultaneously as alignment references, via masks, and air-gap definitions. By combining these functions into a single structuring step, the patent reduces the total number of separate fabrication steps while maintaining high alignment precision for vias and air-gaps.
Solution Approach 2:
The mandrel and spacer structures serve multiple purposes throughout the fabrication process. Mandrels are used for spacer formation and then removed, while spacers define both via positions and air-gap locations. This multi-functionality reduces the need for separate dedicated structures for each feature, streamlining the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of self-aligned vias and air-gaps, reducing resistance and capacitance in current paths, thereby improving the efficiency and alignment of semiconductor devices.
Implementation Method 1
A method that etches a first trench at a first location on a mandrel line in a set of mandrel lines, through a top mask layer and stopping at a middle mask layer
Implementation Method 2
The embodiment fills the fourth trench with a conductive metal to form a self-aligned line-end via on the mandrel line
Implementation Method 3
The embodiment fills the third trench with a low resistance material such that a hollow space is encapsulated within the low resistance material, the hollow space forming the air-gap
Data Source
AI summary
A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.