Self-Aligned M1-M2 Vias for Lower Interconnect RC Delay
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Solution Overview
Problem
As integrated circuit (IC) node sizes shrink, the interconnect resistance/capacitance (RC) delay becomes a significant challenge, dominating total delay time, and existing methods fail to effectively reduce this delay effectively.
Innovation Solution
The method involves forming self-aligned metallization layers and vias using an oversized mask for greater overlay margin and an additional etch step to trim via critical dimensions, resulting in fully self-aligned metallization layers and maximized via metal area to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional interconnect materials and methods are used, then manufacturing process is simple, but interconnect RC delay becomes excessively large
Solution Approach 1:
The patent changes the material parameter from copper to ruthenium, which has higher resistivity but enables better scaling characteristics. It also changes the dimensional parameters by reducing via dimensions and optimizing metallization layer thicknesses to compensate for material resistivity changes, thereby reducing RC delay while maintaining signal transmission performance
2Manufacturing precision
If via dimensions are reduced to maintain scaling, then device density increases, but via resistance increases
Solution Approach 1:
The patent implements self-aligned via formation where the via mask is automatically positioned using the metallization line pattern itself as the reference. This self-service alignment mechanism ensures precise via placement without requiring additional alignment steps, maintaining manufacturing precision while enabling optimized via dimensions that reduce resistance
Solution Approach 2:
The via mask is formed with preliminary dimensional specifications that account for subsequent etching and metallization steps. The mask dimensions are pre-calculated to ensure that after processing, the final via dimensions achieve optimal resistance while maintaining precise alignment with the metallization lines
3Reliability
If overlay margin is increased to improve alignment, then manufacturing robustness improves, but device area increases
Solution Approach 1:
The self-aligned via formation process uses the metallization line pattern itself as the alignment reference, eliminating the need for separate alignment marks and reducing overlay requirements. This self-service approach provides inherent alignment robustness without consuming additional device area for alignment features
Data Source
AI summary
Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.