Self-Aligned Conductive Vias for Back Side Semiconductor Stacking
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Solution Overview
Problem
The alignment of conductive vias in semiconductor components is becoming increasingly difficult due to their smaller size, leading to issues such as misalignment, short circuits, and open circuits during the fabrication process.
Innovation Solution
A maskless back side alignment method is employed, utilizing a polymer deposition and planarization process to form self-aligned conductive vias, eliminating the need for photo masks and ensuring precise alignment without misalignment-related defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photo patterning processes are used to align conductive vias to back side elements, then the fabrication process can be performed with standard equipment, but alignment precision deteriorates due to via size reduction
Solution Approach 1:
The patent applies preliminary action by forming the back side elements (contact pads, conductors, terminal contacts) before forming the conductive vias. This sequence allows the via formation process to self-align to the pre-existing back side elements, eliminating the need for post-via alignment operations and achieving high precision without complex alignment equipment
Solution Approach 2:
The patent inverts the conventional fabrication sequence by forming back side elements first and then forming conductive vias that align to them, rather than the traditional approach of forming vias first and then aligning back side elements. This inversion enables self-alignment and eliminates alignment precision deterioration
2Reliability
If conductive vias are made smaller to meet electrical requirements, then electrical performance is improved, but alignment difficulty increases leading to misalignment defects
Solution Approach 1:
By forming back side elements before conductive vias, the patent enables smaller vias to be formed with precise alignment to the pre-existing back side elements. The via formation process naturally aligns to the contact pads and conductors, preventing misalignment defects even as via dimensions are reduced for improved electrical performance
Solution Approach 2:
The fabrication process employs self-alignment where the conductive via formation process automatically aligns to the pre-formed back side elements without requiring external alignment equipment. This self-service mechanism maintains manufacturing precision even as via size decreases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the fabrication of semiconductor components with conductive vias as small as 10 μm in diameter, preventing short and open circuits, and enabling efficient stacking of components with improved electrical connectivity.
Implementation Method 1
a polymer deposition and planarization process to form self-aligned conductive vias
Implementation Method 2
a polymer deposition and planarization process to form self-aligned conductive vias
Data Source
AI summary
A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.