Self-aligning Conductive Features via Alignment Structures
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Solution Overview
Problem
As semiconductor devices shrink, conductive features connecting layers above and below can become shorted due to misalignment during the etching process, leading to issues with conductive features exposing adjacent conductive features, which existing technologies fail to adequately address.
Innovation Solution
A self-alignment scheme is implemented using alignment structures and spacers on semiconductor devices, allowing conductive features to self-align between layers, ensuring precise alignment and preventing shorting by maintaining a clean inter-layer dielectric layer free from residue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form conductive features, then manufacturing simplicity is maintained, but misalignment occurs causing conductive features to short between layers
Solution Approach 1:
Alignment structures are formed in advance before the conductive features. These pre-formed structures serve as reference markers that guide the subsequent etching process, ensuring that conductive features are etched at the correct positions without requiring complex real-time alignment systems.
Solution Approach 2:
The alignment structures act as intermediary elements between the lithography patterning and the etching processes. They provide a physical reference that mediates the transfer of the pattern from the lithography layer to the conductive feature layer, eliminating direct misalignment between layers.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but alignment precision becomes more critical and harder to maintain
Solution Approach 1:
The alignment system is segmented into separate, independent alignment structures that are formed distinct from the conductive features themselves. This segmentation allows the alignment references to be optimized independently for precision while the conductive features can be optimized for density, decoupling the two requirements.
Solution Approach 2:
The invention changes the physical parameters of the alignment structures, making them larger and more prominent than the conductive features themselves. This parameter change in scale makes the alignment references easily detectable even when the actual features being aligned are extremely small, thus maintaining alignment precision at reduced feature sizes.
3Reliability
If existing alignment methods are used, then process simplicity is maintained, but residue remains on the inter-layer dielectric layer causing alignment issues
Solution Approach 1:
The alignment structures are designed to be temporary fixtures that are completely removed after serving their alignment purpose. This extraction of the alignment function into a separate, removable component prevents any residue from remaining on the inter-layer dielectric layer, as the alignment structures themselves are taken away after use.
Solution Approach 2:
The alignment structures are discarded after use, with their alignment function being recovered through the etching process that uses them as references. The temporary nature of these structures allows them to be discarded without leaving residue, while their alignment function is effectively recovered and transferred to the final conductive feature alignment.
Data Source
AI summary
Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.