Self Aligning Phase Change Memory Device Architecture
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Solution Overview
Problem
The challenge in developing high-density phase change memory devices is the limitation imposed by the array architecture, particularly the need for high reset currents at low voltages, which is difficult to achieve with small phase change material elements and limited contact areas between electrodes and phase change material.
Innovation Solution
A self-aligning memory device architecture is developed, featuring dual word lines and source lines that allow for efficient current distribution, enabling lower voltage operation during reset modes by establishing a lower resistance path through dual conductors, and optimizing the size and spacing of memory elements and access transistors to minimize lithographic constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the phase change material element size is reduced to achieve higher current density, then the reset current magnitude can be reduced, but the contact area between electrodes and phase change material becomes limited, making it difficult to achieve high reset currents at low voltages
Solution Approach 1:
The patent transitions from planar 2D contact geometry to 3D vertical contact geometry by forming contact vias that extend through dielectric layers to reach the phase change material. This vertical dimension allows sufficient contact area for high current delivery while maintaining small lateral footprint for high density integration.
Solution Approach 2:
The patent implements a nested structure where the phase change material element is positioned within a cavity formed in the dielectric layer, and contact vias are nested within the dielectric structure to reach the material. This nesting allows compact integration while maintaining adequate contact dimensions.
2Ease of operation
If access transistors are spaced apart to allow proper operation, then device functionality is maintained, but the array density is limited due to increased spacing requirements
Solution Approach 1:
The patent moves access transistors from a planar 2D layout to a 3D vertical stacking arrangement where transistors are positioned at different heights and connected through vertical vias. This enables closer horizontal spacing while maintaining electrical isolation and proper operation through the vertical dimension.
Solution Approach 2:
The patent combines multiple functions into shared structures, such as using common bit lines and word lines that serve multiple memory cells, and sharing dielectric layers and contact structures between adjacent transistors. This merging reduces the total space required while maintaining individual transistor functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enables the creation of dense, high-capacity memory arrays that can operate at low voltages, facilitating efficient reset operations and reducing the size of memory cells while maintaining high-density integration.
Implementation Method 1
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase.
Implementation Method 2
Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material that differ in the two phases. The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or break down the crystalline structure
Data Source
AI summary
A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width.