Self-Annealing Multi-Die Interconnect Redundancy Control
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Solution Overview
Problem
Conventional redundancy techniques for multi-die interconnect architectures are inflexible and resource-intensive, requiring non-volatile memory for control and leading to performance degradation and increased manufacturing costs due to the need for centralized memory routing and lengthy datapath interconnects.
Innovation Solution
A self-annealing multi-die interconnect redundancy control system using volatile memory to control multiplexing of redundant resources, allowing for local testing and storage of redundancy values, reducing global routing and test time, and enabling continuous evaluation and correction of faulty μbumps without the need for external testers or costly non-volatile memory processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redundancy techniques using non-volatile memory are used, then fault tolerance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the redundancy control function from centralized non-volatile memory and distributes it to individual memory locations throughout the array. Each memory location independently stores and manages its own redundancy information, eliminating the need for complex centralized memory routing and control logic.
Solution Approach 2:
The redundancy control system is segmented into distributed independent units at each memory location rather than a centralized control unit. This segmentation allows each location to autonomously manage its redundancy state, reducing overall system complexity while maintaining fault tolerance capabilities.
2Reliability
If centralized non-volatile memory routing is used, then fault tolerance is improved, but performance degradation occurs due to lengthy datapath interconnects
Solution Approach 1:
The centralized memory routing is segmented into distributed local storage units at each memory location. This eliminates long interconnect paths by placing redundancy control information locally at each location, thereby maintaining fast access speeds while providing comprehensive fault tolerance coverage.
Solution Approach 2:
The patent transitions from a centralized vertical memory hierarchy to a distributed horizontal architecture where redundancy information is embedded at each memory location. This dimensional change eliminates the need for lengthy datapath interconnects while maintaining fault tolerance capabilities.
3Reliability
If conventional redundancy control is used, then fault coverage is improved, but manufacturing cost increases due to non-volatile memory processes
Solution Approach 1:
The patent uses standard volatile memory cells that can be manufactured with conventional CMOS processes instead of expensive non-volatile memory processes. These volatile memory locations serve the redundancy control function adequately without requiring specialized manufacturing, thereby reducing production costs while maintaining sufficient fault coverage.
Solution Approach 2:
The patent makes the existing volatile memory structure multi-functional by using it both for data storage and for redundancy control. This eliminates the need for separate non-volatile memory processes, reducing manufacturing complexity and cost while achieving the required fault coverage through the distributed redundancy mechanism.
Data Source
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AI summary
An apparatus for interconnecting a first die (402) and a second die (404) of a multi-die device (400) includes a master circuit block (406) that interfaces with the first die of the multi-die device, a slave circuit block (408) that interfaces with the second die of the multi-die device, a first memory (416a-416e) in the slave circuit block, a second memory (430a-430e) in the master circuit block, and a plurality of µbumps (1 -6) between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the µbumps (3) as a faulty µbump, and store a first value that corresponds with the identified faulty µbump in the first memory.