Self-Assembled Lithography for Sub-10 Nm Pitch Patterning
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in achieving sub-10 nm pitch patterning, leading to limitations in further scaling and the need for new methodologies or integrated technologies.
Innovation Solution
Advanced pitch patterning techniques and self-assembled device fabrication methods, including spacer-based-patterning schemes, directed self-assembly (DSA) of block copolymers, and iterative spacer formation using atomic layer deposition (ALD), are employed to achieve sub-10 nm devices and structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-10 nm pitch
Solution Approach 1:
The patent applies pitch division techniques that segment the patterning process into multiple stages. First, a mandrel pattern is formed at a relaxed pitch, then spacers are deposited and etched to create additional features between the mandrels, effectively dividing the original pitch into smaller segments. This segmentation enables sub-10 nm precision by breaking down the complex single-step patterning into manageable sequential steps, each operating at a less stringent resolution requirement.
Solution Approach 2:
The patent employs preliminary patterning actions where mandrel structures are formed first at a larger, more manufacturable pitch using conventional lithography. These pre-formed mandrels then serve as templates for subsequent spacer-based patterning that achieves the final sub-10 nm dimensions. This preliminary action allows the most complex dimensional control to be achieved through self-aligned spacer deposition rather than direct lithographic patterning.
2Productivity
If feature size is reduced to increase density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent utilizes self-aligned spacer formation where the spacer width is determined by the conformal deposition thickness rather than lithographic patterning. The spacer automatically aligns to the mandrel sidewalls through self-aligned deposition processes, eliminating the need for separate alignment steps. This self-service mechanism ensures consistent sub-10 nm dimensional control as the spacer width is controlled by atomic layer deposition precision rather than optical resolution limits.
Solution Approach 2:
The patent changes the controlling parameter for feature size from lithographic wavelength and focus to thin film deposition thickness. By controlling the spacer width through atomic layer deposition cycle numbers and precursor dosing, the process achieves precision at the nanometer and sub-nanometer scale that is inaccessible to conventional optical lithography. This parameter change from optical to atomic-scale control enables maintained precision while scaling to higher densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These methods enable the fabrication of semiconductor devices with precise control over feature sizes and pitches, improving dimensional control and allowing for increased density and performance in integrated circuits.
Implementation Method 1
directed self-assembly (DSA) of block copolymers
Implementation Method 2
iterative spacer formation using atomic layer deposition (ALD)
Data Source
AI summary
Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.