Self-Balanced Diode FinFET ESD Protection
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Solution Overview
Problem
Semiconductor devices, particularly FinFETs, are susceptible to high voltage spikes such as electrostatic discharge (ESD) that can cause device failure due to lack of ESD protection mechanisms.
Innovation Solution
A self-balanced diode device is designed with at least one first conductivity type heavily doped fin and multiple second conductivity type heavily doped fins arranged in intersecting directions to form diodes that discharge uniform ESD currents, using an insulation layer and voltage terminals to forward bias the diodes and manage ESD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFETs are used to reduce leakage current, then device reliability is improved, but susceptibility to ESD damage increases due to lack of ESD protection mechanisms
Solution Approach 1:
The patent implements ESD protection diodes formed from heavily doped fins that are pre-configured and integrated into the FinFET structure before ESD events occur. These diodes are ready to immediately divert ESD current away from sensitive circuit elements, preventing damage before it can occur.
Solution Approach 2:
The patent introduces ESD protection diodes as intermediary elements between ESD stress sources and sensitive FinFET circuits. These diodes act as mediators that intercept and redirect harmful ESD current through dedicated discharge paths, protecting the main circuit from direct exposure to ESD spikes.
2Object-affected harmful factors
If conventional ESD protection structures are added to FinFET devices, then ESD protection is improved, but device complexity and integration difficulty increase
Solution Approach 1:
The patent merges ESD protection functionality directly into the FinFET device structure by forming protection diodes using the same heavily doped fin technology. This integration combines ESD protection with the existing device architecture, eliminating the need for separate, complex protection structures and reducing overall device complexity.
Solution Approach 2:
The heavily doped fins serve multiple functions: they form the ESD protection diodes while also being compatible with standard FinFET fabrication processes. This multi-functionality allows the same structural elements to provide both device operation and ESD protection, reducing the need for additional specialized components.
3Productivity
If minimum feature size is reduced to increase integration density, then component integration is improved, but leakage current increases
Solution Approach 1:
The patent replaces planar transistor structures with FinFETs that use vertical fin structures to enhance gate control over the channel. This structural substitution provides stronger electrostatic control, reducing short-channel leakage effects and enabling lower operating voltages that further minimize leakage current while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-balanced diode device effectively reduces semiconductor failures by uniformly discharging ESD currents, enhancing the protection against electrostatic discharge and improving the reliability of semiconductor devices.
Implementation Method 1
at least one first conductivity type heavily doped fin arranged in a line along a first direction and at least two second conductivity type heavily doped fins arranged in a line along a second direction intersecting the first direction to establish at least two diodes which discharge uniform electrostatic discharge (ESD) currents
Implementation Method 2
voltages of the first voltage terminal and the second voltage terminal forward bias the diodes to generate at least two uniform electrostatic discharge (ESD) currents through the diodes
Data Source
AI summary
A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.