Self-Balanced SCR for Uniform ESD Current Distribution
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Solution Overview
Problem
Semiconductor devices, particularly FinFETs, are susceptible to high voltage spikes like electrostatic discharge (ESD) that can cause failures due to increased leakage current and high trigger voltages, which existing technologies have not adequately addressed.
Innovation Solution
A self-balanced silicon-controlled rectification device is designed using N-type and P-type doped wells, heavily doped clamping fins, and heavily doped fins to form silicon-controlled rectifiers (SCRs) that discharge uniform ESD currents, reducing semiconductor failures and lowering the trigger voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET structure is used to reduce leakage current, then leakage current is reduced, but susceptibility to ESD damage increases
Solution Approach 1:
The ESD protection structure is segmented into multiple parallel SCR units, each comprising alternating N-type and P-type doped fins. This segmentation distributes the ESD current across multiple paths, preventing concentration of stress on a single structure and thereby protecting the FinFET while maintaining leakage current reduction.
Solution Approach 2:
The SCR-based ESD protection structure acts as an intermediary between the FinFET and external ESD threats. The SCR triggers at a controlled voltage threshold to divert ESD current away from the sensitive FinFET channel, providing protective mediation without affecting normal operating conditions.
2Reliability
If conventional ESD protection is used, then ESD damage is prevented, but trigger voltage is too high
Solution Approach 1:
The ESD protection structure employs localized heavy doping in specific fin regions to create controlled breakdown characteristics. The N-type and P-type doped fins are strategically positioned with varying doping concentrations to achieve localized field enhancement, enabling lower trigger voltage at specific points while maintaining overall protection effectiveness.
Solution Approach 2:
The invention changes the electrical parameters of the protection structure by using alternating N-type and P-type doped fins with specific doping concentrations. This parameter optimization allows the SCR to trigger at a lower voltage threshold compared to conventional ESD structures, reducing the harmful high trigger voltage effect.
3Reliability
If multiple doped fins are used to form SCR, then ESD current uniformity is improved, but device complexity increases
Solution Approach 1:
Multiple doped fins are merged into a single integrated SCR unit structure where N-type and P-type fins are alternately arranged and electrically connected. This merging approach achieves uniform ESD current distribution across the structure while maintaining a compact design that does not significantly increase overall device complexity.
Solution Approach 2:
The alternating N-type and P-type doped fin structure serves multiple functions simultaneously: it forms the SCR trigger mechanism, provides ESD current distribution paths, and maintains compatibility with standard FinFET fabrication processes. This multi-functionality reduces the need for additional separate components, offsetting the apparent structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces semiconductor failures by uniformly discharging ESD currents and lowering the trigger voltage, enhancing the reliability of semiconductor devices.
Implementation Method 1
voltages of the high voltage terminal and the low voltage terminal forward bias the SCRs to generate a plurality of uniform electrostatic discharge (ESD) currents through the SCRs
Implementation Method 2
ESD is a rapid discharge that flows between two objects due to the built-up of static charge
Data Source
AI summary
A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.