Self-Bias Output Buffer for High Voltage Tolerance
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Solution Overview
Problem
Advanced CMOS processes, such as 28 nm, limit the manufacturing of high voltage devices, causing MOS transistors to be damaged by high voltage signals due to gate oxide breakdown and punch-through, necessitating an output buffer with high voltage tolerance to prevent damage.
Innovation Solution
An output buffer design incorporating a self-bias circuit and cascaded MOS transistors with diodes to regulate voltage differences between electrodes, ensuring they remain below predetermined limits, even when receiving high voltage signals, by providing a bias voltage during both normal and power-down modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced CMOS processes (28 nm) are used to manufacture MOS transistors, then manufacturing precision and integration density are improved, but voltage tolerance deteriorates causing gate oxide breakdown and punch-through at high voltages
Solution Approach 1:
The patent introduces a self-bias circuit as an intermediary component between the high-voltage signal source and the sensitive MOS transistors. This circuit generates a dynamic bias voltage that adapts to the output signal voltage, effectively mediating the voltage stress on the transistors and preventing both gate oxide breakdown and punch-through effects while allowing the advanced CMOS process benefits to be realized
2Adaptability or versatility
If high voltage signals (3.3V) are transmitted to protect compatibility with peripheral components, then adaptability is improved, but MOS transistor damage risk increases due to excessive voltage differences
Solution Approach 1:
The patent employs dynamic biasing where the self-bias circuit continuously adjusts the gate bias voltage in response to the output signal voltage. This dynamic adaptation allows the circuit to maintain full 3.3V compatibility with external devices while simultaneously ensuring that voltage differences across transistor terminals remain within safe operating limits, thus resolving the contradiction between adaptability and damage prevention
3Reliability
If voltage clamping circuits are added to protect MOS transistors from high voltage damage, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-bias circuit that automatically generates the required gate bias voltage without external control signals or additional power supplies. The circuit uses its own output signal and internal transistor configurations to create the protective bias, making the protection mechanism self-regulating and minimizing the addition of external components while maintaining high reliability
Data Source
AI summary
An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.