Self-Biased Current Trimming with RDAC Voltage Scaling

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Solution Overview

Problem

Current reference circuits in analog integrated circuits are sensitive to process, voltage, and temperature (PVT) variations, leading to inaccuracies in current mirroring, especially in low-voltage applications where generating a stable reference voltage is challenging, causing transistors to operate outside the saturation region and degrading current mirroring accuracy.

Innovation Solution

A self-biased current reference circuit using a programmable resistance ladder digital-to-analog converter (RDAC) for voltage trimming, which pre-scales the reference voltage to ensure accurate current mirroring by maintaining the reference transistor deep in the saturation region, and includes a startup circuit to prevent undesired dead states, allowing dynamic voltage scaling through digital input adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional current reference circuit is used, then the circuit structure is simple, but the current mirroring accuracy degrades under PVT variations and low-voltage conditions

Engineering Contradiction:
Improvecurrent mirroring accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamic voltage scaling through a programmable resistance ladder RDAC that adjusts the reference voltage based on digital input codes. This allows the circuit to adapt to different PVT conditions and maintain transistor saturation, thereby improving current mirroring accuracy without requiring a completely static complex structure. The dynamic adjustment capability resolves the contradiction by providing precision only when and where needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter through programmable scaling factors applied to the reference voltage. By modifying the voltage parameter dynamically via the RDAC, the circuit maintains optimal operating conditions for current mirroring across varying PVT conditions. This parameter change approach improves accuracy without permanently increasing structural complexity.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If voltage scaling is applied to maintain transistor saturation, then current mirroring accuracy improves, but the device complexity increases due to additional components

Engineering Contradiction:
Improvecurrent mirroring accuracyVSAvoidcircuit component count
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The resistance ladder RDAC serves multiple functions: it provides voltage scaling, enables digital programmability, and maintains transistor saturation across PVT variations. By making this single component multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity while achieving improved current mirroring accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit includes a self-biasing mechanism where the amplified reference voltage automatically biases the transistors to maintain saturation region operation. This self-service capability reduces the need for external complex biasing circuits, as the reference circuit itself generates the necessary bias conditions, thereby improving accuracy without proportionally increasing complexity.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If a programmable resistance ladder RDAC is used for voltage trimming, then adaptability to PVT variations improves, but the device complexity increases

Engineering Contradiction:
Improveadaptability to PVT conditionsVSAvoidprogrammable circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary calibration during the manufacturing process where the RDAC is programmed with optimal scaling factors before the chips are shipped. This preliminary action establishes the adaptability to PVT variations in advance, eliminating the need for complex runtime adjustment mechanisms and reducing the overall system complexity while maintaining high adaptability to different operating conditions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11237585B2Self-biased current trimmer with digital scaling input
Publication Date: 2022.02.01 MARVELL ASIA PTE LTD
  • US11237585B2 patent drawing
  • US11237585B2 patent drawing
  • US11237585B2 patent drawing

AI summary

In an embodiment, a circuit provided by the present invention includes a transistor connected to allow current to flow from a voltage supply to an output port. The circuit further includes a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor. The RDAC is further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA). The circuit further includes an amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA), and a non-inverting input connected to the output port of the first transistor.