Self-Biased ESD Circuit With Local Ballast for FinFET Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ESD protection circuits in advanced FinFET technologies face challenges with discrete resistors, which provide limited improvement in ESD current handling and lead to early failure due to non-uniform current spreading and hot spots, while also increasing layout footprint.
Innovation Solution
The implementation of local ballast gate (LBG) and local ballast resistor (LBR) mechanisms, which utilize additional transistors and trench/contact layers to provide effective ballast resistance without discrete resistors, improving ESD robustness and reducing layout footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete resistors are used for ESD protection, then current handling capacity is improved, but layout footprint increases and manufacturing complexity increases
Solution Approach 1:
The patent combines the ballast resistor function with the ESD protection circuit by integrating resistive elements directly into the transistor structure (source/drain regions, channel regions) rather than using separate discrete resistors. This merging eliminates the need for additional discrete components while maintaining ESD protection efficacy, thereby reducing layout footprint and manufacturing complexity
Solution Approach 2:
The patent makes the transistor structure serve multiple functions: the source/drain regions and channel regions provide both transistor operation functionality and ballast resistance for ESD protection. This multi-functionality eliminates the need for separate ballast resistors, reducing the overall layout footprint while maintaining current handling capacity
2Reliability
If discrete resistors are used for ESD protection, then current handling capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges the ballast resistance function into the transistor structure itself by utilizing source/drain regions and channel regions with specific resistive properties. This integration eliminates the need for separate discrete resistors and their associated connections, thereby reducing circuit complexity while maintaining ESD protection efficacy
Solution Approach 2:
The transistor structure is designed to perform dual functions: standard transistor operation and ESD protection with built-in ballast resistance. The source/drain regions and channel regions simultaneously provide current conduction and resistive ballasting, simplifying the overall circuit architecture by eliminating separate ballast resistor components
3Reliability
If conventional ESD protection is used, then ESD protection is provided, but current spreading is non-uniform causing hot spots and early failure
Solution Approach 1:
The patent applies local quality by creating non-uniform doping profiles in the source/drain regions and channel regions to achieve uniform current spreading. Specifically, lightly-doped extension regions are positioned to concentrate current in specific areas, while heavily-doped main regions provide low resistance paths. This local variation in doping quality ensures uniform current distribution across the transistor width, preventing hot spots and improving reliability
Solution Approach 2:
The patent changes the electrical parameters (doping concentration, resistivity) of different regions within the transistor structure to optimize current spreading. By adjusting the doping profiles of source/drain extensions and main regions, the patent achieves uniform current distribution across the channel, preventing localized overheating and early failure while maintaining ESD protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These mechanisms enhance ESD performance by increasing voltage robustness and current handling capacity, reducing the risk of thermal failure and layout overhead, while maintaining or improving ESD protection efficacy.
Implementation Method 1
a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit coupled to the first transistor to bias the first transistor such that the first transistor provides ballast resistance during an electrostatic discharge (ESD) event
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.