Self-Biased Isolation for LDMOS Breakdown Voltage
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Solution Overview
Problem
High-side LDMOS devices face breakdown issues between the source and buried isolation layer due to increased field stress when biasing isolation regions at drain voltage, limiting breakdown voltage and compromising electrostatic discharge performance.
Innovation Solution
Implementing self-biased isolation through a structural arrangement that biases isolation regions at a lower voltage than the drain voltage, creating an asymmetric double RESURF effect by using plugs to extend from the substrate to the drift space, thereby reducing electric field stress and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If isolation regions are biased at drain voltage to deplete drift space in double RESURF structure, then breakdown voltage is improved, but field stress between source and buried isolation layer increases causing source-based breakdown
Solution Approach 1:
The device separates the isolation biasing function into distinct components: the buried isolation layer remains at substrate potential while separate isolation regions (first and second isolation regions) are biased at the drain voltage. This segmentation allows the drift space to be depleted for high breakdown voltage while the source-to-buried-isolation path maintains lower field stress.
Solution Approach 2:
The first and second isolation regions act as intermediary structures between the drain voltage and the buried isolation layer. These intermediary regions are biased at drain voltage to deplete the drift space, while the buried isolation layer remains at substrate potential, thus mediating the voltage distribution to prevent direct high-field stress between source and buried isolation layer.
2Strength
If lightly doped buried isolation layer is used to address source-based breakdown, then breakdown voltage is improved, but substrate injection increases and electrostatic discharge performance is compromised
Solution Approach 1:
The device implements different doping characteristics in different regions: the buried isolation layer maintains heavy doping to preserve electrostatic discharge performance and prevent substrate injection, while the first and second isolation regions are configured with appropriate doping to provide depletion when biased at drain voltage. This local quality differentiation resolves the contradiction between breakdown voltage and ESD performance.
3Strength
If double RESURF structure with n-type and p-type regions is implemented, then breakdown voltage is improved through depletion of both regions, but biasing isolation regions at drain voltage increases field stress
Solution Approach 1:
The double RESURF structure is segmented into distinct functional zones: the first isolation region (e.g., n-type) and second isolation region (e.g., p-type) are separated and independently biased at drain voltage to deplete their respective drift spaces, while the buried isolation layer remains at substrate potential. This segmentation enables high breakdown voltage through dual-region depletion while preventing excessive field stress at the source-to-buried-isolation interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively raises the breakdown voltage beyond operational voltages by 15-20V, preventing source-based breakdown and maintaining electrostatic discharge performance, suitable for high-voltage power switching applications.
Implementation Method 1
biasing isolation regions at the drain voltage increases the field stress between the source of the LDMOS device and a buried isolation layer
Implementation Method 2
The RESURF structure is designed to deplete the drift space of the LDMOS device in both vertical and lateral directions
Implementation Method 3
Breakdown resulting from applying such high voltages to the drain is often prevented through a reduced surface field (RESURF) structure of the LDMOS device design. The RESURF structure is designed to deplete the drift space of the LDMOS device in both vertical and lateral directions, thereby reducing the electric field in the PN junctions surrounding the drift region and thus raising the breakdown voltage
Implementation Method 4
Some LDMOS devices have a 'double RESURF' structure, in which the drift space contains both n-type and p-type regions. The double nature of the structure refers to the depletion of the two regions and the reduction of the electric field in the related junction areas
Data Source
AI summary
A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region.