Self-Biased Latch Level Shifter for Signal Droop Prevention
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Solution Overview
Problem
Integrated circuits face challenges in maintaining appropriate common mode voltages at high frequencies and reduced supply voltages, leading to signal droop during long sequences of logical '1' or '0' due to inadequate biasing in level shifter circuits.
Innovation Solution
The implementation of a latch-based level shifter circuit with self-biasing, where each latch node is electrically connected to an input and output node of an inverter, providing a bias voltage to maintain proper common mode voltages and prevent signal droop, even at high frequencies and low supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional level shifter circuits are used without self-biasing, then the circuit structure is simpler, but the common mode voltage cannot be maintained at high frequencies and reduced supply voltages, causing signal droop
Solution Approach 1:
The latch node is electrically connected to an inverter that automatically provides bias voltage to the latch node. This self-biasing mechanism maintains appropriate common mode voltages without requiring external control, enabling the circuit to service itself and maintain signal stability during long sequences of logical '1' or '0' even at high frequencies and reduced supply voltages
2Reliability
If biasing is provided at the latch node, then common mode voltages are maintained at appropriate levels, but the circuit complexity increases due to additional bias circuits
Solution Approach 1:
The inverter connected to the latch node serves multiple functions: it acts as part of the latch circuitry and simultaneously provides the bias voltage through its feedback connection. This multi-functional design maintains common mode voltages appropriately while minimizing additional circuit complexity, as the same component performs both logic and biasing functions
Data Source
AI summary
Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.