Self-Biased NMOS Switch Circuit Without Gate-Limiting Resistors
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Solution Overview
Problem
The existing self-biased gate controlled switching circuit suffers from speed limitations due to current limiting resistors, restricting its applicability in various applications, especially in liquid crystal displays requiring multiple drive levels.
Innovation Solution
The proposed switching circuit incorporates additional transistors and current mirrors to overcome speed limitations without increasing static power consumption, allowing for faster switching and flexibility in voltage differences between supply levels, utilizing back-to-back NMOS transistors and PMOS transistors to manage intermediate voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current limiting resistor is used in the self-biased gate controlled switching circuit, then the circuit can prevent current flow and maintain voltage levels, but the switching speed is limited and reduced
Solution Approach 1:
The patent removes the current limiting resistor from the gate control circuit. Instead of using a resistor to limit current, the circuit uses the inherent output impedance of the current mirror and the body effect of the MOSFET to achieve current limitation, thereby eliminating the speed bottleneck while maintaining voltage level control reliability
Solution Approach 2:
The patent introduces an intermediate voltage node (VINT) and uses it to control the switching of the back-to-back MOSFETs. This intermediary voltage allows the circuit to achieve fast switching by controlling the gate voltages of the MOSFETs through the current mirror, which naturally limits current without requiring an external resistor
2Speed
If additional transistors and current mirrors are added to increase switching speed, then the switching performance improves, but the static power consumption increases
Solution Approach 1:
The patent designs the current mirror and transistor network to be dynamically controlled by the enable signal. During normal operation, the circuit operates at high speed with the current mirror actively controlling the gate voltages. When disabled, the circuit transitions to a low-power state where the transistors are turned off, eliminating static power consumption while maintaining fast switching capability when enabled
Solution Approach 2:
The patent changes the operating parameters of the transistors based on the enable signal state. When enabled, the transistors operate in saturation mode for fast switching. When disabled, the bias conditions are changed to cut-off mode, reducing static power consumption to near zero while preserving the fast switching capability for when the circuit is needed
Data Source
AI summary
A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.