Self-Biased PLL Bandwidth Tuning Under PVT Variations
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Solution Overview
Problem
Existing Phase Locked Loops (PLLs) face challenges in adjusting loop bandwidth and are susceptible to process, voltage, and temperature (PVT) variations, limiting their flexibility and stability.
Innovation Solution
A self-biased PLL design that includes a bias current generator with adjustable parameters, such as reference voltage and frequency, allowing for dynamic adjustment of loop bandwidth through a bias current that is proportional to these parameters, while maintaining stability by using an active resistor in the loop filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the loop bandwidth is adjusted by changing circuit parameters (resistance and capacitance values), then the loop bandwidth can be modified, but the PLL loses flexibility for further adjustments and becomes stable only at fixed parameters
Solution Approach 1:
The patent changes the control parameter from fixed circuit parameters (R and C values) to adjustable bias current. By modifying the bias current supplied to the charge pump, the loop bandwidth can be dynamically adjusted without changing the physical circuit parameters, thus maintaining both adaptability and stability.
Solution Approach 2:
The patent introduces bias current as an intermediary parameter that mediates between the control signal and the loop bandwidth. Instead of directly changing resistance or capacitance values, the bias current serves as a controllable intermediary that adjusts the charge pump current, thereby adjusting the loop bandwidth while keeping the circuit structure stable.
2Adaptability or versatility
If the charge pump current is adjusted to achieve wider loop bandwidth, then the loop bandwidth increases, but it becomes difficult to achieve programmable current in fractions and the adjustment becomes unstable
Solution Approach 1:
The patent changes the control approach from directly adjusting charge pump current to adjusting bias current. This parameter change enables fine-grained control through fractional adjustments of the bias current (e.g., 1/2 or 1/4), making programmable current control practical and stable while achieving the desired loop bandwidth adjustment.
3Area of stationary object
If device size is scaled down to reduce chip area, then the chip size decreases, but the impact of PVT variations on PLL design increases
Solution Approach 1:
The patent introduces dynamic bias current adjustment capability that allows the PLL to adapt to PVT variations in real-time. By dynamically adjusting the bias current based on operating conditions, the system compensates for the increased sensitivity to PVT variations that results from device scaling, thereby maintaining reliability in smaller chip areas.
Data Source
AI summary
A self-biased Phase Locked Loop (PLL) is provided. The self-biased PLL includes a bias current generator configured to generate a bias current Ib, wherein the bias current Ib includes one or more adjustable parameters for adjusting a loop bandwidth wn of the self-biased PLL. The one or more adjustable parameters in the bias current Ib includes at least one of a reference voltage Vref and a reference frequency Fref.