Self-Biased Power-Down Circuit for Stable Gated-VDD

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Solution Overview

Problem

Conventional power-providing schemes for integrated circuits using gated power supplies suffer from significant variations in gated-VDD due to fluctuations in current through diodes, process variations, and temperature changes, leading to potential malfunctions such as data loss in memory circuits.

Innovation Solution

A novel power supply circuit that includes a first power supply node, a gated-node, and control devices to manage voltage drops, with a negative-feedback current source and voltage-controlled current source to track and compensate for variations in gated-voltage, using PMOS and NMOS transistors and diodes in parallel to stabilize the voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If a diode is used to generate gated-VDD by dropping voltage from VDD, then power consumption is reduced in low-performance operations, but the gated-VDD varies significantly due to current fluctuations, process variations, and temperature changes

Engineering Contradiction:
Improvepower consumptionVSAvoidgated-VDD stability
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where a compensation current is generated based on the actual gated-VDD voltage and fed back to adjust the diode current. This closed-loop control stabilizes the gated-VDD by compensating for variations caused by current fluctuations, process differences, and temperature changes, while maintaining the power-saving benefit of voltage gating

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters of the diode by dynamically adjusting its current based on feedback from the actual gated-VDD measurement. By varying the diode current to compensate for voltage deviations, the system maintains stable gated-VDD output despite variations in operating conditions, thereby resolving the stability issue while preserving energy efficiency

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the current through the diode is increased to reduce voltage drop variation, then gated-VDD stability improves, but power consumption increases

Engineering Contradiction:
Improvegated-VDD stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent dynamically adjusts the diode current parameter based on actual gated-VDD measurements rather than using a fixed high current. The compensation mechanism allows the system to use only the necessary current to maintain stability, optimizing the trade-off between power consumption and voltage stability by adapting the current parameter to actual operating conditions

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If process corners vary (SS vs FS), then circuit performance changes, but gated-VDD becomes unpredictable and may cause malfunctions

Engineering Contradiction:
Improveprocess corner coverageVSAvoidgated-VDD predictability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent employs feedback to measure the actual gated-VDD voltage and generate compensating current based on deviations from the target voltage. This approach makes the system adaptive to different process corners (SS, FS, etc.) by automatically adjusting operating parameters to maintain predictable and stable gated-VDD output across all process variations, eliminating the need for separate designs for each corner

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution reduces variations in gated-VDD and gated-VSS, enhancing the performance and reliability of integrated circuits by stabilizing the power supply voltage, as demonstrated by a 26.3% reduction in variation compared to conventional circuits, improving operation across different process corners.

Implementation Method 1

A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.

Methodology Applied
Scientific EffectNegative feedback: Feedback

Implementation Method 2

A voltage-controlled current source is connected in parallel with the diode, wherein the voltage-controlled current source includes an input node. A gated voltage-tracking circuit including an output is connected to the input node of the voltage-controlled source.

Methodology Applied
Scientific EffectVoltage control:

Data Source

PatentUS7760009B2Power-down circuit with self-biased compensation circuit
Publication Date: 2010.07.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7760009B2 patent drawing
  • US7760009B2 patent drawing
  • US7760009B2 patent drawing

AI summary

A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.