Self-Biased RF Switch Circuit Reducing Control Complexity
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Solution Overview
Problem
Stacked antenna RF switches require complex control circuitry to manage gate and body bias, leading to increased complexity and real estate usage on chips, while existing solutions do not efficiently address the need for simpler control mechanisms.
Innovation Solution
A self-biased N-type metal-oxide-semiconductor (NMOS) is coupled to both gate and body bias to control the ON/OFF states of the RF switch, with the NMOS body in a floating connection configuration to improve conductivity and reduce insertion loss, and electrostatic discharge (ESD) isolation is maintained by not connecting the NMOS to any die bumps of the integrated circuit package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex control circuitry is used to manage gate and body bias of stacked antenna RF switches, then the switch performance (linearity, insertion loss, power handling) is improved, but the device complexity and chip real estate usage increase
Solution Approach 1:
The patent implements self-biasing circuitry that automatically generates the required gate and body bias voltages without external control signals. The self-biasing network uses the RF switch's own operating conditions to produce the necessary bias voltages, eliminating complex external control circuitry while maintaining proper switch performance characteristics including linearity and insertion loss
Solution Approach 2:
The patent combines multiple bias generation functions into a single integrated self-biasing network. The body bias and gate bias are generated together through a unified circuit architecture that shares common components, reducing the overall control circuitry complexity and chip real estate requirements while maintaining the necessary bias control for optimal RF switch performance
2Ease of operation
If separate control signals are used for gate and body bias, then precise control of RF switch states is achieved, but the control circuitry becomes more complex and consumes more chip area
Solution Approach 1:
The self-biasing network performs multiple control functions simultaneously - generating both body bias and gate bias voltages, providing isolation control, and maintaining proper operating points for the RF switch. This multi-functional approach eliminates the need for separate control signal paths, reducing chip real estate while maintaining precise control over switch states
Solution Approach 2:
The patent introduces a self-biasing network as an intermediary that automatically generates the necessary bias voltages based on the RF switch's operating conditions. This intermediary circuit eliminates the need for complex external control signal generation while maintaining precise control over the switch states, effectively mediating between the RF switch and external control circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the control circuitry, reduces insertion loss, and maintains isolation, thereby addressing the complexity and space constraints of existing RF switch control systems.
Implementation Method 1
A self-biased N-type metal-oxide-semiconductor (NMOS) is coupled to both gate and body bias to control the ON/OFF states of the RF switch
Implementation Method 2
with the NMOS body in a floating connection configuration to improve conductivity and reduce insertion loss
Data Source
AI summary
A wireless communication device can include switch circuitry. The switch circuitry can include stacks having a common gate node and a common body node, wherein a stack includes a metal-oxide-semiconductor field-effect transistor (MOSFET) having a body resistive element coupled to a body terminal of the MOSFET and the common body node a gate resistive element coupled to a gate terminal of the MOSFET and the common gate node. The switch circuitry can further include a self-biased MOSFET coupled to the common gate node and the common body node, a gate of the self-biased MOSFET configured to receive direct current (DC) bias with a low pass filter.