Self-Calibrated Multiphase Clock Generation for Low-Noise LO Phases
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Solution Overview
Problem
Existing multi-phase clock generation devices for harmonic rejection mixers require high-speed clock sources, leading to high electric current consumption and noise, especially in applications like NFC systems where low-order band-pass filters are insufficient for attenuating unwanted LO harmonics.
Innovation Solution
A multi-phase clock generation device with a self-calibration unit that generates phase-shifted clock signals using a reference clock, reducing electric current consumption by disabling self-calibration after initial calibration, and employing trimmable delay elements and phase comparators for accurate phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed clock source is used to generate multiple LO phases for accurate delay, then the phase accuracy and harmonic rejection performance is improved, but the electric current consumption and noise increase significantly
Solution Approach 1:
The patent changes the operating parameters by using a single-phase clock at a lower frequency instead of a high-speed clock, and compensates for the delay inaccuracies through calibration. This transforms the approach from relying on high frequency to relying on calibrated delay elements, thereby reducing power consumption while maintaining phase accuracy.
Solution Approach 2:
The patent replaces the mechanical/high-frequency clock system with a calibrated delay element system. Instead of using a high-speed clock to achieve accurate delays, the system uses programmable delay elements that are calibrated to provide accurate phase shifts at a lower clock frequency, thus reducing power consumption and noise.
2Measurement precision
If a high-speed clock source is used to generate multiple LO phases, then the phase accuracy is improved, but the noise generation increases
Solution Approach 1:
The patent changes the clock frequency parameter from high to low, and compensates through calibration of delay elements. This parameter change reduces the noise generated by the clock source while maintaining phase accuracy through the calibration process.
3Measurement precision
If DLL-based multi-phase clock generation is used, then phase accuracy can be achieved, but the electric current consumption is high due to continuous operation of calibration circuitry
Solution Approach 1:
The patent performs the calibration action preliminarily - once at startup or when needed - and then stores the calibration data. The calibrated delay elements are then used without requiring continuous calibration operation, thus achieving phase accuracy while significantly reducing power consumption during normal operation.
Solution Approach 2:
The system performs self-calibration automatically at startup or when required, and then operates autonomously using the stored calibration data. This self-service approach eliminates the need for continuous external calibration, reducing power consumption while maintaining accuracy.
Data Source
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AI summary
Multiphase clock generation device (100), comprising: - an input (1) for feeding a reference clock (CLKp0); - a clock generation unit (10) adapted to generate phase-shifted clock signals from the reference clock (CLKp0); - a phase comparator unit (20) functionally coupled with the clock generation unit (10), wherein the phase comparator unit (20) is adapted to measure a phase shift (ε) of the phase-shifted clock signals; and - a self-calibration unit (30) functionally coupled with the clock generation unit (10), wherein the calibration unit (30) outputs a delay-calibration parameter (dset) to the clock generation unit (10), wherein the clock generation unit (10) is adapted to generate a multiphase clock signal (CLKMP) out of the reference clock (CLKp0) and the delay-calibration parameter (dset).