Self-Calibrating DAC With On-Chip Resistor Mismatch Trimming
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Solution Overview
Problem
High-precision digital-to-analog converters (DACs) face challenges in achieving accurate output due to resistor mismatch errors, which are difficult to fabricate and require external components and trimming for error correction, especially in modern systems demanding high accuracy.
Innovation Solution
A self-calibrating DAC design that includes a least significant bit (LSB) and most significant bit (MSB) resistor network with trimmable resistors, using a resistance-to-frequency converter and a comparator to generate trimming signals, allowing for on-chip calibration without an external analog-to-digital converter, thereby correcting resistor mismatches and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If external components and post-manufacture trimming are used for error correction, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration function into the DAC chip itself by integrating a calibration DAC, resistor network, and control logic. This eliminates the need for external trimming components and post-manufacture adjustment circuits, thereby reducing device complexity while maintaining manufacturing precision through on-chip self-calibration
Solution Approach 2:
The DAC performs self-calibration using an internal calibration DAC and resistor network. The system automatically measures and corrects its own non-linearity errors through digital processing, eliminating the need for external calibration equipment and manual trimming operations, thus reducing device complexity while maintaining high manufacturing precision
2Manufacturing precision
If a precision DAC is used to fine-tune gain and offset, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces the need for additional precision DAC components with a digital calibration algorithm that processes output data from the main DAC. By using digital signal processing to calculate and correct non-linearity errors, the system achieves high signal precision without adding complex analog precision DAC circuitry
Solution Approach 2:
The calibration DAC serves multiple functions: it generates test signals for calibration, provides reference voltages for error measurement, and enables self-diagnosis of the main DAC. This multi-functional approach achieves high signal precision without requiring separate dedicated precision components
3Ease of manufacture
If resistor networks are used for DAC implementation, then ease of manufacture is improved, but manufacturing precision deteriorates due to resistor mismatch
Solution Approach 1:
The patent implements a feedback-based calibration system that measures the actual output of the DAC and uses this information to calculate correction factors. The system feeds back the measured non-linearity errors and applies digital corrections to compensate for resistor mismatches, thereby maintaining ease of manufacture with standard resistor networks while achieving high manufacturing precision through active error compensation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-precision DAC calibration without external components, reducing die size and achieving accurate digital-to-analog conversion by continuously trimming resistors to match their values, thereby minimizing integral non-linearity and other errors.
Implementation Method 1
A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network
Data Source
AI summary
A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.