Self-Clocked Comparator Circuit for Low-Power Clock Distribution
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Solution Overview
Problem
Existing comparator circuits in liquid crystal display devices require many large buffers for clock signal transmission, leading to high power consumption and difficulty in reducing it.
Innovation Solution
A self-clocked comparator circuit that generates a self clock signal based on its own output, eliminating the need for an external clock signal and reducing the requirement for buffer circuits, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external clock signal is used for the comparator circuit, then the clock signal transmission is reliable, but many large buffers are required leading to high power consumption
Solution Approach 1:
The comparator circuit generates its own self clock signal using its output signal and matching signal, eliminating the need for external clock buffers. The clock generation circuit creates the clock signal internally based on the comparator's own operations, making the system self-sufficient and reducing power consumption while maintaining reliability
2Reliability
If external clock buffers are used, then clock signal distribution is ensured, but device complexity increases
Solution Approach 1:
The external clock buffer component is extracted and removed from the system. The comparator circuit no longer requires external clock buffers for signal distribution, as the self clock signal is generated internally, thereby reducing device complexity while maintaining clock signal distribution functionality
Solution Approach 2:
The clock generation function is merged into the comparator circuit itself. The clock generation circuit is integrated with the comparator, combining the clock generation and comparison functions into a single unit, eliminating separate buffer circuits and reducing overall device complexity
Data Source
AI summary
A comparator circuit according to the present embodiment: including a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit including a data input terminal to which a constant potential is supplied and a clock input terminal and configured to hold a value of the data input terminal based on a self-clock signal input to the clock input terminal; and a clock generation circuit configured to generate the self-clock signal based on the matching signal.