Self-Clocked Generator for Asynchronous Processor Latency Control
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Solution Overview
Problem
Asynchronous processing systems face challenges in managing variable processing latencies and avoiding meta-stability, which can lead to processing delays and hazards, particularly in the absence of a global clock-tree, requiring innovative solutions for handshaking protocols and latency management.
Innovation Solution
The implementation of a self-clocked asynchronous processing system with configurable self-clocked generators that produce clocking signals based on predetermined delays, allowing each processing stage to operate independently and manage its own latency, thereby eliminating the need for a global clock-tree and reducing meta-stability risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a global clock-tree is used in synchronous systems, then system stability and coordination are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the global clock-tree from the system, extracting the timing coordination mechanism from the synchronous architecture. Each processing stage uses its own self-clocked generator that is triggered by the completion signal from the previous stage, eliminating the need for a centralized clock distribution network while maintaining stable operation through local timing control.
Solution Approach 2:
The system is divided into independent self-timed processing stages, each with its own self-clocked generator. This segmentation allows each stage to operate autonomously with its own timing control, triggered by the completion signal from the previous stage, thereby eliminating the global clock-tree while maintaining system coordination.
2Stability of the object's composition
If a fixed clock cycle is used in synchronous systems, then system coordination is improved, but processing flexibility and adaptability worsen
Solution Approach 1:
The patent implements dynamic timing control where each self-clocked generator can be configured with different time periods based on the specific processing operations. The instruction dispatcher determines the appropriate time period for each operation type, allowing the system to adapt to varying processing requirements while maintaining coordination through the completion signal protocol.
Solution Approach 2:
The system changes the timing parameter dynamically based on the operation type. Different operations have different required time periods, and the self-clocked generators are configured accordingly through the instruction dispatcher, which selects the appropriate time period from predetermined options based on the operation being performed.
3Device complexity
If processing stages wait for fixed clock cycles, then system simplicity is improved, but processing delay and throughput worsen
Solution Approach 1:
The patent enables continuous processing by allowing the next stage to begin processing as soon as the current stage completes, without waiting for a fixed clock cycle. The completion signal immediately triggers the self-clocked generator of the next stage, creating a continuous pipeline that eliminates idle waiting time and maximizes throughput.
Solution Approach 2:
The instruction dispatcher determines the appropriate time period for each operation in advance and configures the self-clocked generators accordingly. This preliminary configuration allows processing stages to be ready and immediately begin work when triggered, eliminating delays that would occur with fixed clock cycles where stages must wait for the next clock edge.
4Adaptability or versatility
If asynchronous processing is implemented, then processing flexibility and power efficiency are improved, but system stability and hazard management worsen
Solution Approach 1:
The patent implements a feedback mechanism where the completion signal from each processing stage serves as the trigger for the next stage's self-clocked generator. This feedback loop ensures that processing stages operate in sequence without creating hazards, as each stage must complete its operation and generate a completion signal before the next stage can be triggered, thereby maintaining system stability while preserving asynchronous flexibility.
Data Source
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Figure 2
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AI summary
A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.