Self-Clocking Comparator Stabilizing Charge Pump at Low Current

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Solution Overview

Problem

Charge pumps face challenges in operating efficiently at low current levels, particularly when the supply voltage is low, as they tend to oscillate and become unstable due to delays in comparator outputs, limiting the current that can be provided.

Innovation Solution

A self-clocking comparator is introduced, featuring multiple gain stages and a reset circuit that oscillates the compare voltage between two levels based on the difference between the sense voltage and reference voltage, allowing for faster clock rates without increasing static current consumption, thereby stabilizing the charge pump output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If the comparator output delay is reduced to prevent charge pump oscillation, then the stability of the charge pump is improved, but the current consumption of the comparator increases

Engineering Contradiction:
Improvecharge pump stabilityVSAvoidcomparator current consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The reset circuit proactively resets the gain stages before the comparator output can change state due to delay, preventing the charge pump voltage from excursions that would cause oscillation. By anticipating and preventing the instability condition rather than reacting to it, the system maintains stability without requiring a faster (and more power-consuming) comparator.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The reset circuit acts as an intermediary between the comparator output and the gain stages, inserting a control mechanism that prevents the harmful effects of comparator delay. This intermediary reset signal ensures the gain stages are in the correct state before the comparator output transitions, decoupling the stability requirement from the comparator speed requirement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the capacitor switching frequency is increased to provide more current from the charge pump, then the current output capability is improved, but the voltage excursion increases causing oscillation and instability

Engineering Contradiction:
Improvecharge pump current outputVSAvoidcharge pump stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The reset circuit monitors the comparator output state and provides feedback control to the gain stages. When the comparator output transitions to indicate the charge pump output has fallen below the reference voltage, the reset circuit activates to ensure proper gain stage state, creating a feedback mechanism that stabilizes operation even at high switching frequencies and current outputs.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If the comparator delay is increased to reduce current consumption, then the comparator power usage is reduced, but the charge pump output voltage oscillates and becomes unstable

Engineering Contradiction:
Improvecomparator power consumptionVSAvoidcharge pump output stability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The reset circuit performs preliminary action by resetting the gain stages in advance before the comparator output transition occurs. This proactive reset ensures the gain stages are properly conditioned to handle the upcoming output transition, preventing oscillation even with the delayed comparator response associated with low power consumption.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9553572B2Self clocking comparator for a charge pump
Publication Date: 2017.01.24 SILICON LABORATORIES INC
  • US9553572B2 patent drawing
  • US9553572B2 patent drawing
  • US9553572B2 patent drawing

AI summary

A self clocking comparator for clocking a charge pump providing a high voltage output including multiple gain stages and a reset circuit. The gain stages are configured to assert the compare voltage at a first voltage level in a default state when the sense voltage is greater than the reference voltage, and to assert the compare voltage to a second voltage level in a reset state when the sense voltage falls below the reference voltage. The reset circuit resets, or otherwise forces, the gain stages back to the default state in response to the compare voltage transitioning to the second voltage level. The compare voltage oscillates while the sense voltage is less than the reference voltage at a frequency based on a magnitude of a difference between the sense voltage and the reference voltage up to a predetermined maximum frequency level.