Single-Line Self-Clocking Signal Encoding at Full Bit Rate
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Solution Overview
Problem
Existing signal protocols require separate clock signals for synchronization, leading to inefficient bandwidth usage and increased complexity due to the transmission of both clock and data information, with self-clocking protocols only conveying information using half of the bit rate.
Innovation Solution
A self-clocking transmission signal protocol that encodes clock information and data payload in a single line using a unipolar non-return-to-zero line, where an initial pulse width defines the clock frequency, and subsequent pulses indicate data payload with edge transitions representing bit changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate clock signal is transmitted with the data signal, then synchronization accuracy is improved, but bandwidth efficiency deteriorates and device complexity increases
Solution Approach 1:
The patent combines the clock signal and data signal into a single transmission line. The encoder generates a unified signal that embeds both timing information (clock) and data information, eliminating the need for separate transmission lines. This merging approach maintains synchronization accuracy while improving bandwidth efficiency by utilizing the full bit rate of a single channel.
Solution Approach 2:
The single transmission line serves multiple functions: it simultaneously conveys clock timing information and data payload. The signal protocol is designed so that the same line that carries data also carries synchronization information, making the transmission system multi-functional and eliminating the need for dedicated clock lines.
2Measurement precision
If a separate clock signal is transmitted with the data signal, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock signal generation and data encoding into a single integrated process at the encoder, and similarly combines clock recovery and data decoding at the receiver. This reduces the number of separate components and signal lines required, thereby simplifying the overall transmission system while maintaining synchronization accuracy.
3Device complexity
If self-clocking protocol is used, then device complexity is reduced, but information transmission rate deteriorates to half bit rate
Solution Approach 1:
The patent employs periodic transitions in the signal to encode both clock timing and data information. By utilizing every transition (both rising and falling edges) to represent data bits, the system achieves full bit rate transmission. The periodic nature of the signal transitions provides self-clocking capability while maximizing the information carried per unit time.
Solution Approach 2:
The patent changes the encoding parameters to utilize both edges of clock transitions for data representation. Instead of using only one edge (which would limit rate to half bit rate), the system employs bidirectional edge encoding where both rising and falling transitions carry information, thereby doubling the effective transmission rate while maintaining self-clocking properties.
Data Source
AI summary
A signal encoding and decoding protocol to transmit both clock information and a data payload in a single line is disclosed. Data may be encoded in a unipolar non-return-to-zero line in which an initial pulse width determines a clock frequency, followed by a series of pulses indicating the data payload. Each clock transition following an initial synchronization pulse indicates a data bit in which the value of the bit is determined in relation to the previous bit. Edge information may indicate a change in bit value from the previous bit. If the transmission signal remains at the same level for a subsequent clock period, the bit value remains the same.