Self-Contained Subframe Carrier Aggregation for Low-Latency Modem Processing
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Solution Overview
Problem
The deployment of 5G NR technology with large spectrum and low latency requirements creates a processing bottleneck and peak hardware demand, leading to increased hardware and energy consumption without optimal utilization.
Innovation Solution
Implementing carrier aggregation techniques to process component carriers with different timing characteristics, interleaving symbols for efficient pipeline processing without increasing hardware capacity, and optimizing acknowledgment timing to meet latency targets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If large spectrum (greater than 100 MHz) is deployed in 5G NR with low latency requirements, then bandwidth and data transmission capability are improved, but receiver processing operations create a peak processing bottleneck that increases hardware capacity requirements and power consumption
Solution Approach 1:
The patent segments the processing of code blocks into multiple stages using a pipeline architecture, where different processing steps (demodulation, decoding, etc.) are performed in sequence across multiple hardware stages. This allows continuous processing of multiple code blocks simultaneously at different stages, eliminating the need for peak processing capacity and reducing power consumption while maintaining high bandwidth utilization.
2Speed
If additional hardware capacity is added to meet latency targets in large spectrum deployments, then processing capability is improved, but hardware costs and power consumption increase
Solution Approach 1:
The patent implements a continuous pipeline processing architecture where multiple code blocks are processed simultaneously at different stages. While one code block is being demodulated, another is being decoded, and a third is being prepared for transmission. This continuous utilization of hardware resources maintains high processing speed without requiring additional peak capacity, thereby reducing hardware quantity and power consumption.
3Reliability
If hardware capacity is increased to handle peak processing demands, then latency targets are met, but hardware utilization is low for majority of the time
Solution Approach 1:
The patent employs a dynamic pipeline processing system that adapts to varying data loads by continuously processing multiple code blocks through different stages. The pipeline maintains optimal utilization by keeping all hardware stages actively working on different portions of data simultaneously, ensuring high and consistent hardware utilization while reliably meeting latency targets without over-provisioning.
Data Source
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AI summary
The present disclosure provides for enhanced pipeline processing using different timing characteristics for aggregated carriers. A receiving device may receive a first component carrier and a second component carrier from a transmitting device during a subframe including a first set of symbols on the first component carrier and a second set of symbols on the second component carrier. The first component carrier may be a priority component carrier having a different timing characteristic than the second component carrier. The receiving device may process, using a hardware processing pipeline, the first set of symbols interleaved with the second set of symbols. The receiving device may transmit an acknowledgment, within the subframe, based on the processing of at least all of the first set of symbols.