Self-Converged Void Bottom Electrode for Phase Change Memory
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Solution Overview
Problem
Existing phase change memory devices face limitations in reducing the magnitude of the reset current required for transitioning from a crystalline to an amorphous state, which is constrained by the minimum feature size of manufacturing equipment, leading to non-uniformity and unreliability in high-density memory devices.
Innovation Solution
The method involves creating a self-converged void and bottom electrode within a dielectric material using a keyhole opening process, allowing for the deposition of a dielectric material and electrode material to form a memory cell with a small active region, thereby reducing the size of the phase change material element and minimizing the reset current needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the size of the phase change material element is reduced to minimize reset current, then the magnitude of reset current is reduced, but the manufacturing precision and uniformity deteriorate due to minimum feature size constraints of manufacturing equipment
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical structuring by forming tapered keyhole openings and self-converged voids. This dimensional change allows the active phase change region to be confined vertically within the dielectric layer, achieving sub-lithographic dimensions that are not constrained by conventional 2D photolithography resolution limits.
Solution Approach 2:
The patent employs self-converged void formation where the void automatically tapers and converges to a small aperture at the top surface through controlled deposition processes. This self-organizing behavior creates the desired sub-lithographic structure without requiring additional lithography steps, enabling precise dimensional control that overcomes manufacturing equipment feature size limitations.
2Productivity
If conventional manufacturing processes are used to create small memory cells, then the minimum feature size of manufacturing equipment limits the cell size, but using smaller cells is needed to achieve higher current densities
Solution Approach 1:
The patent achieves sub-lithographic dimensions by moving from 2D planar patterning to 3D vertical structuring. The keyhole opening and self-converged void create a tapered structure where the smallest dimension (aperture at top surface) is achieved through vertical deposition control rather than lateral lithography, bypassing the minimum feature size constraint and enabling higher current density in smaller effective areas.
Solution Approach 2:
The patent changes the controlling parameter for dimension from lateral lithography resolution to vertical deposition thickness and taper angle. By controlling the deposition parameters (such as atomic layer deposition cycles and etch rates), the aperture size and void geometry can be precisely tuned to achieve the desired small dimensions for high current density without being limited by lithography equipment capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacture of memory cells with sub-lithographic dimensions, achieving higher current densities with smaller absolute current values, enhancing the reliability and uniformity of high-density memory devices.
Implementation Method 1
A dielectric material is deposited into the keyhole opening to create a second memory cell subassembly comprising a void within the deposited dielectric material
Implementation Method 2
An electrode material is deposited into the electrode hole and in contact with the electrically conductive element to create a third memory cell subassembly
Data Source
AI summary
A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer.