Self-Correcting Latch Circuit for SEU Error Correction
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Solution Overview
Problem
Conventional latch designs, despite incorporating redundancy for error correction, are still susceptible to multiple single-event upsets (SEUs) over time, which can lead to incorrect outputs, and may have significant overhead in terms of physical size, speed, and power consumption, making them costly and inefficient.
Innovation Solution
A self-correcting latch design that loads values into at least three stages, uses a not-equal gate to detect errors, and feeds the latch circuit output back to the inputs for reloading, allowing for rapid correction of SEUs within one system clock cycle, and optionally includes a majority gate for enhanced reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional latch designs incorporate redundancy for error correction, then reliability is improved, but device complexity and physical overhead increase
Solution Approach 1:
The latch is divided into multiple stages (first latch stage, second latch stage, third latch stage) that operate sequentially within a single clock cycle. This segmentation allows the circuit to perform multiple functions (storage, error detection, correction, and reloading) in a structured manner, achieving high reliability without excessive complexity
Solution Approach 2:
The latch circuit automatically detects errors using the not-equal gate and performs self-correction by reloading the correct value from the output back to the inputs. This self-service mechanism eliminates the need for external error correction control, reducing device complexity while maintaining high reliability
2Reliability
If conventional latch designs incorporate redundancy for error correction, then reliability is improved, but speed decreases
Solution Approach 1:
The latch circuit continuously monitors for errors and performs correction within the same clock cycle without interrupting the overall system operation. The feedback path enables continuous reloading of correct values, ensuring that error correction is an ongoing process rather than a discrete interrupt, thereby maintaining high speed
Solution Approach 2:
The correction process is completed rapidly within a single clock cycle by skipping intermediate steps that would otherwise require multiple cycles. The direct feedback path from output to input allows the circuit to rush through the correction process efficiently, achieving correction times within 25-500 picoseconds
3Reliability
If conventional latch designs incorporate redundancy for error correction, then reliability is improved, but power consumption increases
Solution Approach 1:
The latch performs error detection and correction autonomously using the not-equal gate and feedback mechanism, eliminating the need for external control logic. This self-service approach reduces the overall power consumption of the system while maintaining reliable error correction capability
Solution Approach 2:
The latch circuit performs error correction periodically within each clock cycle rather than continuously or through multiple separate cycles. This periodic action optimizes power consumption by activating correction only when needed (when errors are detected) while maintaining system reliability
Data Source
AI summary
A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).