Self-Correcting Phase-Locked Loop for PDC Transfer Function Drift
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Solution Overview
Problem
Existing all-digital phase-locked loops (ADPLLs), particularly Phase-to-Digital Converter ADPLLs, face challenges in maintaining a stable phase-to-digital transfer function due to variations in process, voltage, and temperature (PVT), leading to changes in delay element propagation delay, gain mismatches, and offset mismatches, which affect the loop's performance and locking time.
Innovation Solution
A novel correction circuit within the Phase-to-Digital Converter ADPLL that processes first phase error words to generate second phase error words, normalizing the phase-to-digital transfer function by adjusting multiplier values to compensate for delay element variations, gain mismatches, and offset mismatches, ensuring the slope remains constant and independent of PVT changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay line is used in the phase-to-digital converter to measure phase difference, then phase measurement capability is achieved, but propagation delay variations due to PVT changes cause transfer function slope changes
Solution Approach 1:
The patent implements a feedback mechanism where the measured phase differences are used to dynamically adjust the delay element delays. The controller monitors the phase measurement results and modifies the delay line characteristics to compensate for PVT variations, ensuring the transfer function slope remains constant despite environmental changes.
Solution Approach 2:
The patent changes the delay parameters of the delay elements dynamically based on operating conditions. By adjusting the delay amounts in response to measured phase differences and PVT conditions, the system maintains a constant transfer function slope while preserving phase measurement capability across varying temperatures, voltages, and process conditions.
2Reliability
If delay element delays are adjusted to compensate for PVT variations, then transfer function stability is improved, but additional control circuitry increases device complexity
Solution Approach 1:
The system performs self-calibration by using its own phase measurement capability to detect PVT variations and automatically adjust its delay elements. The controller uses the measured phase differences as feedback to self-correct the transfer function slope without requiring external calibration equipment or complex manual adjustment mechanisms.
Solution Approach 2:
The delay elements serve multiple functions: they provide the primary delay for phase measurement and simultaneously act as adjustable compensation elements for PVT variations. The same delay line structure is used for both measurement and calibration purposes, reducing the need for separate compensation circuitry.
3Speed
If the loop divider divides by a large integer N, then frequency division ratio is achieved, but the period of DIV_OUT becomes much longer than HCLK, making delay chain design unworkable
Solution Approach 1:
The patent transitions from measuring phase differences using a single long delay chain to using multiple shorter delay elements with adjustable delays. By distributing the total delay across multiple stages and making each stage adjustable, the system achieves the required frequency division ratio without requiring an impractically long single delay chain.
Solution Approach 2:
The patent segments the delay measurement function into multiple adjustable delay elements rather than using a single long delay chain. Each delay element can be independently adjusted to compensate for PVT variations, and their combined delays achieve the required frequency division ratio while keeping individual element delays within practical limits.
4Speed
If high frequency HCLK signal is supplied to inverter chain for TDC operation, then frequency synthesis capability is achieved, but current consumption becomes undesirably high
Solution Approach 1:
The patent replaces the analog inverter chain mechanism with a fully digital delay element structure. Instead of using high-frequency switching inverters that consume significant current, the system uses digital delay elements controlled by the phase-to-digital converter, achieving frequency synthesis capability with reduced power consumption.
Data Source
AI summary
A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function.