Self-Enabled Bus Contention Detection Circuit
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Solution Overview
Problem
Conventional bus contention detection circuits have low detection accuracy due to restricted internal threshold ranges and require additional enable signals, leading to inadequate detection in cases of manufacturing defects or core logic failures.
Innovation Solution
A self-enabled bus contention detection circuit comprising a delay unit, a duty cycle adjustment unit, and a comparison unit, which generates and processes signals to determine bus conditions without external enable signals, improving detection accuracy by comparing voltage levels with a reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional receiver modules with threshold ranges are used for bus contention detection, then the detection circuit can identify bus conditions, but the detection accuracy is limited due to restricted internal threshold ranges
Solution Approach 1:
The patent changes the detection parameter from voltage threshold comparison to duty cycle comparison. The duty cycle adjustment unit converts the contention detection problem into a time-domain measurement, where the duty cycle of the output signal directly reflects the bus contention state. This parameter transformation eliminates the need for multiple threshold ranges while maintaining high detection accuracy.
2Reliability
If additional enable signals from core logic are required for the detection circuit to operate, then the circuit can be controlled, but the applicability is restricted and the circuit fails when core logic fails
Solution Approach 1:
The detection circuit uses the bus signal itself as the input to generate the enable signal through the delay unit and duty cycle adjustment unit. This self-service mechanism eliminates the need for external enable signals from core logic, allowing the circuit to operate independently and reliably even when core logic fails or is unavailable.
Solution Approach 2:
The delay unit acts as an intermediary that processes the input signal to generate both the timing reference and the enable signal for the comparison unit. This intermediary mechanism decouples the detection circuit from core logic dependencies while maintaining proper timing relationships.
3Adaptability or versatility
If the detection circuit operates without additional enable signals, then the applicability and reliability improve, but the circuit must self-generate timing and enable signals
Solution Approach 1:
The delay unit performs multiple functions: it generates the timing reference signal, creates the enable signal for the comparison unit, and establishes the correct phase relationship between input and output signals. This multi-functionality reduces the need for separate signal generation circuits while improving adaptability.
Data Source
AI summary
A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for receiving a reference voltage, and an enable terminal for receiving an enable signal of the duty cycle adjustment unit. The enable signal has a rising edge that is delayed relative to a rising edge of the output signal and a falling edge that is aligned with a falling edge of the output signal. The comparison unit compares a voltage level of the output signal with the reference voltage when the enable signal is in a stable voltage state and determine a bus condition in response to a comparison result.