Self Evaluation Engine for Multi-Core SoC Testing
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Solution Overview
Problem
Testing and characterization of complex digital integrated circuits with multiple cores, such as SoCs, is challenging due to increased complexity and cost, as conventional methods require extensive input pattern testing, which becomes prohibitively expensive and inefficient.
Innovation Solution
A Self Evaluation Engine (SEE) is implemented on each core to create a quality metric or partial good value by executing tests and comparing characterization signatures with neighboring cores, producing a partial good status for the entire SoC, thereby reducing testing time and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deterministic testing methods are used to test every possible input pattern, then testing completeness is improved, but testing cost and time increase prohibitively
Solution Approach 1:
The patent applies partial action by testing only a subset of input patterns rather than all possible combinations. The Built-In Self-Test (BIST) logic generates pseudorandom test patterns and uses signature comparison to determine pass/fail status, performing sufficient testing to detect defects without exhaustively testing every possible input combination, thereby reducing test time and cost while maintaining adequate reliability
Solution Approach 2:
The patent uses signature comparison where the output signature of the device under test is compared against a pre-stored good signature. This copying approach allows rapid verification without re-running complete test sequences, as the expected behavior is captured and reused for comparison, significantly improving testing efficiency
2Reliability
If multiple microprocessor cores are included in SoC design, then functional redundancy and yield are improved, but testing complexity and cost increase
Solution Approach 1:
The patent segments the testing process by providing separate BIST logic and signature comparison capabilities for each core. Each core can be independently tested and characterized, allowing the complex multi-core system to be broken down into manageable test units. This segmentation reduces overall testing complexity while maintaining the ability to test all cores systematically
Solution Approach 2:
Each core includes built-in self-test logic that allows it to test itself autonomously without requiring external test equipment to control each core individually. The BIST logic within each core generates test patterns and the signature comparison logic evaluates results, enabling cores to self-diagnose their functional status and reducing the complexity of external testing infrastructure
3Loss of time
If pseudorandom input test patterns are used instead of deterministic testing, then testing time is reduced, but testing precision decreases
Solution Approach 1:
The patent uses periodic application of pseudorandom test patterns with signature comparison at regular intervals. The LFSR generates sequences at fixed periods and the signature is captured and compared periodically, providing systematic defect detection throughout the test process while maintaining rapid pacing that limits test time
Solution Approach 2:
The patent replaces deterministic mechanical testing approaches with pseudorandom pattern generation and signature comparison. Instead of systematically applying every possible input combination (mechanical/deterministic approach), the system uses pseudorandom sequences combined with cryptographic-style signature comparison, achieving comparable defect detection with significantly reduced test time
Data Source
AI summary
A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.