Self-Formed Barrier Metal Layer for CMP-Friendly Interconnects
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Solution Overview
Problem
The advancement of semiconductor technology makes it challenging to fabricate interconnect structures using pure metal materials like tungsten, cobalt, or copper, as CMP control becomes increasingly difficult, leading to the use of alloys with a large mean free path to reduce grain boundary scattering. However, these alloys pose challenges during the CMP process, requiring innovative solutions to manage oxidation and planarization effectively.
Innovation Solution
The method involves forming a self-formed barrier metal layer by depositing an alloy with a relatively active and noble metal element mixture, followed by CMP processes that oxidize the active element and selectively remove the metal oxide, allowing the noble element to form a barrier layer, which can serve as an etch stop or be used to create hybrid metal structures within interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pure metal materials like tungsten, cobalt, or copper are used for interconnect structures, then electrical conductivity is improved, but CMP control becomes increasingly difficult
Solution Approach 1:
The patent uses composite material structures including alloy materials (such as cobalt-platinum, cobalt-iridium) instead of pure metals. These composite interconnect structures maintain good electrical conductivity while providing superior CMP controllability, as the alloy composition allows for optimized polishing characteristics compared to pure metal materials.
Solution Approach 2:
The patent changes material parameters by using alloys with specific compositions (e.g., cobalt with 1-20% platinum or iridium) to alter the physical and chemical properties. This parameter modification enables better CMP process control while maintaining electrical performance, resolving the contradiction between conductivity and manufacturability.
2Reliability
If alloys with large mean free path are used to reduce grain boundary scattering, then electrical resistance is reduced, but oxidation control during CMP becomes challenging
Solution Approach 1:
The patent introduces a barrier metal layer (such as tantalum, tantalum nitride, or tungsten nitride) as an intermediary between the alloy interconnect and the dielectric material. This barrier layer prevents oxidation of the alloy during CMP processing while maintaining the electrical benefits of the low-resistance alloy material.
Solution Approach 2:
The patent extracts the oxidation-prone alloy material from direct exposure to the CMP environment by placing it within a protective structure consisting of the barrier metal layer. This separation allows the alloy to provide low electrical resistance without suffering from oxidation issues during manufacturing.
3Manufacturing precision
If additional etch stop layers are deposited to enable precise etching, then etching precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent makes the barrier metal layer serve multiple functions: it acts as both an oxidation barrier during CMP and as an etch stop layer for subsequent etching processes. This multi-functionality eliminates the need for separate etch stop layers, reducing manufacturing complexity while maintaining etching precision.
Solution Approach 2:
The patent merges the barrier metal layer and etch stop layer into a single functional layer. The barrier metal (tantalum, tantalum nitride, or tungsten nitride) combines the oxidation protection function with the etch stop function, simplifying the overall structure and reducing the number of deposition steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient planarization and reduces the need for additional etch stop layers, saving time and cost in semiconductor manufacturing by utilizing the self-formed metal oxide layer for etching and forming reliable interconnects with reduced electrical resistance.
Implementation Method 1
performing a planarization treatment on the first metal material using a slurry that includes an oxidizing agent to form a metal oxide layer and a barrier metal layer on the first metal material
Data Source
AI summary
A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.