Self-Forming 2D Interconnect Barriers for Sub-10 Nm Scaling
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling multi-gate transistors to sub-10 nm dimensions due to constraints on performance and variability, limiting further miniaturization and integration of functional components in integrated circuits.
Innovation Solution
The implementation of linerless self-forming barriers, specifically using two-dimensional crystalline layers formed from conductive materials like copper, tungsten, or cobalt, which act as both fill material and barrier, eliminating the need for separate liner or barrier deposition, thereby minimizing space and resistance in interconnects and enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing compatibility and cost are maintained, but manufacturing precision and performance deteriorate at sub-10 nm dimensions
Solution Approach 1:
The conductive fill material automatically forms a barrier layer through self-diffusion into the dielectric material, eliminating the need for separate liner or barrier deposition processes. This self-forming mechanism achieves precise barrier formation at sub-10 nm dimensions while simplifying the fabrication process.
Solution Approach 2:
The barrier layer and conductive fill material are merged into a single integrated structure where the conductive material serves dual purposes: as the interconnect fill and as the barrier layer. This consolidation reduces the number of fabrication steps while maintaining precise dimensional control.
2Reliability
If separate liner or barrier deposition is used, then barrier protection is achieved, but interconnect space and resistance increase
Solution Approach 1:
The barrier function and conductive fill are merged into a single material system, eliminating the need for separate liner layers. The conductive material diffuses directly into the dielectric to form the barrier, reducing total interconnect space while maintaining barrier protection.
Solution Approach 2:
The conductive fill material self-organizes to form the barrier layer at the interface with the dielectric material, creating a precise, thin barrier without requiring additional deposition steps. This self-forming barrier minimizes interconnect dimensions while ensuring adequate protection.
3Reliability
If separate liner or barrier deposition is used, then barrier protection is achieved, but fabrication complexity and costs increase
Solution Approach 1:
The barrier deposition and conductive fill operations are merged into a single process step, eliminating multiple fabrication stages. The conductive material simultaneously provides both the barrier function and the interconnect conductivity, reducing overall process complexity.
Solution Approach 2:
The barrier layer forms automatically through the self-diffusion of the conductive fill material into the dielectric material, eliminating the need for separate liner or barrier deposition processes. This self-organizing mechanism simplifies fabrication while ensuring reliable barrier protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance integrated circuit structures with increased transistor width and improved gate control, stability, and performance, suitable for future technology nodes, while reducing fabrication complexity and costs.
Implementation Method 1
The 2D crystalline liner can prevent diffusion of copper atoms into a dielectric material
Implementation Method 2
upon formation of the 2D crystalline liner by a forming gas anneal
Data Source
AI summary
Integrated circuit structures having linerless self-forming barriers, and methods of fabricating integrated circuit structures having linerless self-forming barriers, are described. In an example, an integrated circuit structure includes a dielectric material above a substrate. An interconnect structure is in a trench in the dielectric material. The interconnect structure includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the dielectric material and with the conductive fill material. The 2D crystalline liner includes a same metal species as the conductive fill material.