Self-Gated Pulse-Triggered Clock Gating Cell for Power Loss Reduction
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Solution Overview
Problem
Conventional clock gating cells experience power loss due to continuous switching of the clock signal at the clock input stage, leading to repetitive charging and discharging of capacitive loads, even when storage elements do not need to change their states.
Innovation Solution
A clock gating cell design that includes a latch circuit, comparison logic circuit, and multiple logic circuits to generate a gated clock signal by switching the input clock signal only when necessary, based on the comparison of input and output signals, thereby reducing continuous switching at the clock input stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous clock signal is provided to storage elements, then the storage elements can change states when needed, but power loss occurs due to repetitive charging and discharging of capacitive load
Solution Approach 1:
The patent extracts the unnecessary continuous clock signal from the clock input stage by introducing a gating mechanism. The gated clock signal is generated by ANDing the input clock signal with a gate signal, effectively removing the continuous switching that causes power loss while preserving the functionality needed for state changes.
Solution Approach 2:
The patent transforms the continuous clock signal into a periodic gated clock signal that switches states only when necessary. The gate signal controls when the clock signal is allowed to pass through, creating periodic action only when state changes are required, thereby reducing unnecessary charging and discharging cycles.
2Loss of energy
If a clock gating cell is introduced to reduce power loss, then power consumption decreases, but the device complexity increases due to additional logic circuitry
Solution Approach 1:
The patent merges the clock gating functionality with the existing latch circuit structure. The gated clock signal generation is integrated into the latch circuit by using the same logic gates (AND gate, inverters) that are already present in the latch, thereby reducing overall device complexity while achieving power loss reduction.
Solution Approach 2:
The patent makes the logic circuitry multi-functional by using the same gates for both latch operation and clock gating. The AND gate and inverters serve dual purposes: controlling the latch state and generating the gated clock signal, thereby reducing the need for additional dedicated gating circuitry.
3Speed
If the clock signal switches continuously at the clock input stage, then the latch circuit can respond to clock edges, but continuous charging and discharging of capacitive load causes power loss
Solution Approach 1:
The patent introduces a gated clock signal as an intermediary between the input clock signal and the latch circuit. This intermediary signal preserves the essential clock edges needed for latch response while filtering out continuous switching that causes power loss, thereby maintaining speed while reducing energy consumption.
Data Source
AI summary
A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.