Self-Gated Level Shifter Circuit for Low-Power Voltage Conversion
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Solution Overview
Problem
RFID systems face challenges in efficiently converting digital input signals with lower high logic levels to output signals with higher high logic levels, particularly in RFID tag ICs, where different circuit blocks operate at different supply voltages, requiring a level shifter circuit to enable communication between them.
Innovation Solution
A level shifter circuit is designed using a PMOS latch circuit and a current mirror circuit, with the current mirror assisting the latch circuit during transitions to provide a digital output signal with a higher high logic level, and includes self-gated transition amplifier circuits to reduce power consumption and facilitate switching between logic levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a level shifter circuit is used to convert digital input signals with lower high logic levels to output signals with higher high logic levels, then communication between circuit blocks operating at different supply voltages is enabled, but power consumption increases
Solution Approach 1:
The circuit performs preliminary action by pre-charging the output node through the current mirror circuit before the actual switching transition occurs. This reduces the power required during the main switching event and enables level conversion with lower overall power consumption.
Solution Approach 2:
The patent introduces an intermediary current mirror circuit that mediates between the input latch and output. This current mirror acts as a power-efficient interface that transfers the logic state from the lower voltage domain to the higher voltage domain without requiring direct high-power switching at the output node.
2Adaptability or versatility
If a level shifter circuit converts digital input signals to output signals with higher high logic levels, then communication between circuit blocks is enabled, but the circuit complexity increases
Solution Approach 1:
The patent merges the latch circuit and current mirror circuit into a single integrated level shifter unit. By combining these functions in one compact circuit block, the design achieves level conversion capability without proportionally increasing overall system complexity, as the merged structure shares common transistors and control signals.
Solution Approach 2:
The level shifter circuit is designed with multi-functionality, serving both as a latch element and as a level conversion interface. The same circuit structure can handle different voltage levels and support bidirectional communication, reducing the need for separate dedicated circuits for each function.
Data Source
AI summary
A level shifter circuit configured to convert a digital input signal with a first high logic level to a digital output signal having a second high logic level substantially higher than the first high logic level is provided. The level shifter circuit may include a PMOS latch circuit configured to receive the digital input signal and having first and second latch outputs and a current mirror circuit having a mirror input and a mirror output. The mirror input may be at least partly gated by a switch having a control input. The mirror output may be coupled to the first latch output. The control input may be coupled to the first or second latch outputs, and the digital output signal is provided from the first and/or second latch outputs.