Self-Healing Compute Array With 3D Bonded Memory
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Solution Overview
Problem
Conventional compute arrays for AI, ML, and DSP applications face challenges in achieving small size, low power consumption, and cost-effectiveness due to the high area overhead of monolithic memory solutions and excessive power usage of external memory chips, especially in battery-powered devices.
Innovation Solution
The implementation of face-to-face (F2F) or wafer-to-wafer (W2W) bonding of memory arrays within compute arrays, allowing memory to be integrated or relocated, and exploiting self-healing properties to route around defective units, thereby reducing size, power consumption, and costs while maintaining array integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If monolithic memory solutions (eSRAM or eDRAM) are integrated with compute arrays, then memory access speed and integration are improved, but area overhead and manufacturing cost increase substantially
Solution Approach 1:
The patent segments the memory system into multiple independent memory chips rather than using a single monolithic memory array. Each memory chip can be independently optimized and manufactured, reducing the area overhead per compute unit while maintaining fast access speeds through parallel memory operations and proximity placement.
Solution Approach 2:
The patent transitions from a planar 2D integration approach to a 3D stacked architecture where memory chips are vertically positioned above compute array chips. This dimensional change enables high-density memory integration with fast access while minimizing the footprint area on each chip layer.
2Area of stationary object
If external memory chips are used with compute arrays, then area overhead is reduced, but power consumption and interface complexity increase to unacceptable levels
Solution Approach 1:
The patent implements a nested hierarchy where small high-speed memory buffers are integrated within each compute unit, which are then nested within larger memory chips that are vertically stacked above the compute array. This multi-level nested structure provides both area efficiency and low power consumption by minimizing data transfer distances at each hierarchy level.
Solution Approach 2:
The patent introduces intermediate memory buffers and controllers that mediate between the compute units and external memory chips. These intermediaries reduce the power consumption of data transfers by pre-fetching and caching data locally, reducing the frequency and volume of high-power external memory accesses.
3Ease of manufacture
If conventional compute arrays are manufactured without self-healing capability, then manufacturing process is simpler, but yield and reliability decrease due to defective units
Solution Approach 1:
The patent implements preliminary self-diagnosis and self-healing actions that are built into the compute array architecture before deployment. Test circuits and routing mechanisms are pre-configured to detect defective units during manufacturing testing and automatically reconfigure the array to bypass defects, ensuring high yield and reliability without complicating the manufacturing process.
Solution Approach 2:
The patent enables the compute array to perform self-diagnosis and self-healing operations autonomously. The array monitors its own units for defects and automatically reconfigures routing to bypass faulty components, eliminating the need for external repair interventions and maintaining high reliability while keeping the manufacturing process relatively simple.
Data Source
AI summary
This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.