Self-Hibernating Memory System Power Latency Tradeoff
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Solution Overview
Problem
Flash memory devices face power conservation challenges due to current leakage issues, especially in portable electronic devices, where complete power termination to conserve energy results in latency penalties and compromised power savings, as RAM must remain awake to handle host requests, thereby consuming significant current.
Innovation Solution
A memory system that enters hibernation mode upon detecting a lull in host commands, storing controller state data in non-volatile memory and reducing power to volatile storage, allowing for immediate restoration when host commands are received, with the ability to signal command completion before protocol timeouts by buffering data and using pointers to guide state data retrieval, thus minimizing power usage without affecting host operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If complete power termination is applied to flash memory device to conserve energy, then power consumption is reduced, but latency increases due to full mount requirement
Solution Approach 1:
The system performs preliminary actions by maintaining controller state data in non-volatile memory during active periods, so that upon entering standby mode, the data is already prepared and can be quickly restored without requiring a full mount sequence, thus reducing latency while conserving power
Solution Approach 2:
The invention extracts the controller state data from volatile RAM and stores it in non-volatile memory, separating the data persistence function from the volatile storage. This allows the RAM to be powered down while the controller state is preserved externally, enabling both power savings and quick recovery
2Speed
If RAM remains awake to handle host requests in standby mode, then response time is improved, but power consumption increases due to significant current usage
Solution Approach 1:
The non-volatile memory acts as an intermediary between the host interface and the controller state data. It maintains the controller state persistently without requiring continuous power to RAM, while the host interface can still receive and process commands by restoring necessary state from non-volatile memory, thus enabling power savings without completely sacrificing responsiveness
Solution Approach 2:
The system prepares controller state data in non-volatile memory during active operation, so that when standby mode is entered, the data is already in place and can be quickly restored to RAM upon receiving host requests, enabling fast response without maintaining continuous power to the full system
3Reliability
If controller state data is fully restored from non-volatile memory upon receiving host command, then data integrity is ensured, but response time exceeds host protocol timeout
Solution Approach 1:
The system applies partial action by restoring only the necessary portion of controller state data from non-volatile memory that is required to handle the specific host command, rather than restoring the entire controller state. This selective restoration approach maintains data integrity for the needed operations while significantly reducing the time required to respond to host requests, keeping response times within protocol timeouts
Data Source
AI summary
A memory system self-initiates hibernation mode and responds to host commands issued during hibernation within a host protocol timeout period. Hibernation mode is entered after controller state data has been stored and while no host command to the memory system is pending. Power to volatile data storage is diminished during hibernation mode. Upon receiving a host command during hibernation mode, power is restored and a reduced portion of the controller state data is read from non-volatile memory. A removable data storage device or a portable electronic device with embedded data storage may be constructed with such a self-hibernating memory system.